Superconducting Technology Assessment - nitrd

6.2.3. 3-D PACKAGING – ISSUES AND CONCERNS
Minimal thermal resistance is critical for superconducting electronic applications where the components need to
operate at 4 K. Other trade-offs associated with 3-D packaging are:
■ Cost.
■ Test.
■ Reparability.
Testing of the complex 3D system-in-stack requires further development and better understanding of the system
design. Added complexity will result from the high clock speed of SCE-based systems.
Another major issue (similar to secondary packaging) is the availability of a foundry. A dedicated and independent
packaging foundry is critically needed for SCE-based applications. It is assumed that this foundry can be co-located
with the MCM foundry.
6.2.4 3-D PACKAGING – ROADMAP AND FUNDING
A roadmap for the development of 3D packaging for SCE is shown in the figure below. The funding profile needed
to maintain development pace is listed in Table 6-3. The funding assumes that the foundry is co-located with the
MCM foundry. More details are presented in Appendix L: Multi-Chip Modules and Boards. (The full text of this
appendix can be found on the CD accompanying this report.)
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I. 3-D
trade -
offs
1.
3-D
Req
docu
ment
2. 3-D Process
Development
3. 3-D Test
Vehicle
Design
4. 3-D Foundry
Fabrication and Qual
2.
3-D
Test
Vehicle
8-16
layers
10
Gbps
5. 3-D Test Vehicle
Fabrication and
Qual
- -
7. Prototype
3-D Design
3.
3-D Process
and Foundry
qualified
8-16 layers
10 Gbps
8. Prototype
3-D Fab and
Test
4.
3-D
Prototype
16-32
layers
50Gbps
MILESTONES
5.
3-D
Prototype
qualified
16-32 layers
50 Gbps
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