Superconducting Technology Assessment - nitrd

Execution Models
Organizing hardware for an RSFQ-based supercomputer is one thing, but how do we organize processing and
software to maximize computational throughput? The widely used approach of manually structuring software to
use message passing communications is far from optimal; many applications use synchronizing “barrier” calls that
force processors to sit idle until all have entered the barrier. Similarly, the overlapping of computation with
communications is often inefficient when done manually.
Execution models are the logical basis for maximizing throughput, while system hardware architecture provides the
physical resources to support the execution model. Hardware architectures not tied to an execution model are
unlikely to support optimal throughput; conversely, execution models that ignore hardware constraints are unlikely
to be efficiently implemented. Mainstream parallel computers tend towards a message-passing, SPMD (single
program, multiple data) execution model and hardware architecture with a homogeneous set of processing nodes
connected by a regularly structured communications fabric. (The physical structure of the fabric is not visible to the
programmer.) This execution model was developed to handle systems with tens to hundreds of processing nodes,
but computational efficiencies decrease as systems grow to thousands of nodes. Much of the inefficiency appears
due to communications fabrics with insufficient bandwidth.
There have been a number of machines developed to explore execution model concepts. Some of these—most
notably the Thinking Machines CM-1 and the Tera MTA — were developed for commercial use; unfortunately, both
of these machines were successful in achieving their technical goals but not their commercial ones.
The HTMT study is noteworthy in that the conceptual execution model was developed to match the hardware
constraints described above, with the added notion that multi-threading was a critical element of an execution
model. The conventional SPMD approach could not be mapped to the hardware constraints, nor could
multi-threading alone define the execution model. The solution was to reverse the conventional memory access
paradigm: instead of issuing a memory request and waiting for a response during a calculation, the HTMT execution
model “pushes” all data and code needed for a calculation into the very limited memory of the high-speed processors
in the form of “parcels.” Analytical studies of several applications have demonstrated that the execution model
should give good computational throughput on a projected petaflops hardware configuration.
While little data is yet publicly available, both the IBM and Cray HPCS efforts appear to be co-developing execution
models and hardware architectures. The IBM PERCS project is “aggressively pursuing hardware/software co-design”
in order to contain ultimate system cost. The Cray Cascade project incorporates an innovative hardware architecture
in which “lightweight” processors feed data to “heavyweight” processors; the execution model being developed
has to effectively divide workload between the lightweight and heavyweight processors. Extensive use of simulation
and modeling is being carried out to minimize the risk associated with adopting an innovative architecture.
While there is some research into execution models for distributed execution (Mobile Agent models, for example),
there is little research on execution models for large-scale supercomputers. The Japanese supercomputing efforts
(NEC and Fujitsu) have focused on engineering excellence rather than architecture innovation. The GRAPE
sequence of special-purpose supercomputers uses an execution model designed to optimize a single equation on
which N-body simulations depend.
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