Superconducting Technology Assessment - nitrd

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For system-in-stack purposes, it was necessary to develop a technique to be able to stack packaged components and/or bare die components. This technique creates uniform size layers with non-uniform die sizes in each layer by creating a frame around the die (or dice) using potting as shown in Figure 4. Process starts with a bumped KGD encapsulated in a potting compound. Thin film metal traces contact the I/O bumps and route the signals to the edges of the potting material. The layer is ground from the backside resulting in a thin (100-250 micron) complete layer. The stack is created by laminating many layers with a cap substrate, which uses through-holes to provide I/O paths. Metalization is applied on one or more sides to interconnect layers and the cap substrate. System-in-stacks with heterogeneous mix of components and the needed discretes for the high-speed operation of the stack can be realized. Multi-layer traces can be used to support complex interconnect structures needed for multi-chip layers and for high-speed operation up to 30 GHz. Heat management layers (such as copper, diamond, etc.) can be added on top of active components. These layers have dual functions: ■ Providing a low-resistance, direct path for efficient thermal flow to the edge of the stack to keep the maximum temperature in the stack under control. ■ Serving as shims to maintain the total layer-to-layer tolerances of the stack for high-density edge interconnect structures. The manufacturability is maintained by allowing loose tolerances in the layer formation (component height variations, substrate thickness variations). Heterogeneous 3D chip stacking is a versatile technology allowing stacking of non-electronic components. Waveguides, vertical cavity surface emitting lasers, detectors are among devices used in stack layers. The free surfaces of the stacks are especially suitable for these types of devices. Optical interconnects from stack to stack and integrated focal plane arrays were already demonstrated 4 . <strong>Superconducting</strong> electronic circuits based on NbN and Nb Josephson junctions were inserted in stack layers and operated at temperatures as low as 4 K indicating the flexibility and reliability of the material system used in 3D chip stacks (Figure 5). Stacked systems were operated at 20 GHz. There are proposed approaches to integrate MEMS devices and passive optical components in stacks. When the material selection and system design is judiciously performed, chip stacks have been shown to operate reliably with MTTF exceeding 10 years, in a wide temperature range (from – 270 C to 165 C) and in hostile environments subjected to 20,000 G. 3D packaging provides an excellent alternative to satisfy the needs high functionality system and sub-system integration applications, yielding system architectures that cannot be realized otherwise. Thermal management is a key issue when aggressive miniaturization is used to pack large electronic functionalities into small volumes. When the power budget increases, thermal management layers can be inserted in the stack as alternating layers in addition to active layers. Experimental and analytical results indicated that up to 80W can be dissipated in a stack volume of 1cm 3 . Thermal resistance within the stack can be as low as 0.1 C/W. Minimal thermal resistance is critical for superconducting electronic applications where the components need to operate at 4 K. Other trade-offs associated with 3D packaging are: ■ Cost. ■ Test. ■ Reparability. 4 V. Ozguz, P. Marchand, Y. Liu, Proc. International Conference on High Density Interconnect and System Packaging, (2000), p. 8 231
We must note that the reparability is a common issue for each high-level integration approaches including VLSI. Testing of the complex 3D system-in-stack requires further development and better understanding of the system design. Added complexity will result from the high clock speed of SCE-based systems. Figure 4. Heterogeneous stacking technology for system-in-stack. Figure 5. Stacks containing superconducting electronics circuits were cycled from RT to 4 K several times; surviving 570 C temperature excursion. High speed operation was demonstrated up to 20 GHz in test layers. 232 IC Water Support Matrix Embedded Neo-Chip 3d Stacked Module Dice � � Leads Gold Connection Bus Potting Compound Matrix Mounted Chips Gold Trace First Layer Potting Compound Gold Trace First Layer Potting Compound Silicon Blank Gold Trace Second Layer Gold Bump Large Chip (thinned) Gold Bump Chips (thinned) Polyimide Polyimide Silicon Blank
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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Structurally, a high-end computer w
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16 ■ Chalmers University in Swede
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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MCMs The design of MCMs for SCE chi
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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Circuits/ Organizations Flux-1/ NG,
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3.1.2 RSFQ PROCESSORS - READINESS F
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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4.6 ROADMAP AND FACILITIES STRATEGY
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Figure 4-6. Timeline for developmen
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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98 Data Communication Requirement R
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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6.2. 3-D PACKAGING Conventional ele
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
Page 193 and 194: Speed and Density The first planned
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Page 197 and 198: Appendix I
Page 199 and 200: Table 1 Representative Nb and NbN-B
Page 201 and 202: ground plane may be located either
Page 203 and 204: Fig. 4. Junction fabrication proces
Page 205 and 206: Table 6 Junction Array Summary of T
Page 207 and 208: Fig. 11. Ground plane planarization
Page 209 and 210: B. Yield Yield measurements are an
Page 211 and 212: Fig. 17. Photograph of the FLUX-1r1
Page 213 and 214: [47] B. Bumble, H. G. LeDuc, J. A.
Page 215 and 216: Appendix J
Page 217 and 218: Fig. 2. The Schematic View describe
Page 219 and 220: Fig. 4. The VHDL View captures the
Page 221 and 222: Fig. 6. LMeter is specialized softw
Page 223 and 224: Fig. 8. Layout-versus-Schematic ver
Page 225 and 226: Appendix K
Page 227 and 228: 1. CURRENT STATUS OF OPTICAL INTERC
Page 229 and 230: 1.2. CURRENT OPTICAL INTERCONNECT R
Page 231 and 232: If technology, power, or cost limit
Page 233 and 234: 3.4 COARSE VS. DENSE WAVE DIVISION
Page 235 and 236: 3.5 DEVELOPMENTS FOR LOW TEMPERATUR
Page 237 and 238: 5. ROADMAP The roadmap below shows
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Page 241 and 242: The bandwidth, chip density and int
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Page 247 and 248: Figure 7. A typical cryocooler encl
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Page 251 and 252: Although cooling of the 4 K circuit
Page 253 and 254: Supplying DC current to all of the
Page 255 and 256: These properties enable the possibi
Page 257: For additional copies, please conta
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