Superconducting Technology Assessment - nitrd

Fig. 17. Photograph of the FLUX-1r1 microprocessor chip
fabricated in NGST’s 4-kA/cm process. The chip is 1 cm on a
side, contains $63 000 junctions, and dissipates 9 mW. The inset
represents the potential reduction in chip size if the FLUX chip is
redesigned in a 20-kA/cm process.
Table 8
Nb Technology Roadmap
for petaFLOPS scale computing. Semiconductor technology
has scaled by 0.7 in feature size and 2.5 in gate density for
each generation, each of which has taken about three years
and a substantial capital investment. Beyond the present 8- to
10-kA/cm processes, continued evolutionary improvements
in niobium technology will require only relatively modest investment
in new process tools and facilities.
IX. CONCLUSION
Because of its extreme speed advantage and ultralow
power dissipation, superconductor electronics based on
RSFQ logic will eventually find widespread use in high-performance
computing and in applications that need the fastest
digital technology such as analog-to-digital converters and
digital signal processing. To be a viable commercial digital
technology, the superconductor electronics community must
demonstrate systems that operate at higher speeds with lower
power than any other technology. Process development efforts
are pushing the boundaries of niobium technology in
three key areas: increasing speed, increasing complexity,
and increasing yields. Rapid progress has been achieved in
the past few years, driven by the high-performance computing
initiative. In addition to advancements in fabrication,
the superconductor electronics community needs to focus
attention on standardization of test and design tools. Finally,
building complete systems or subsystems, which have taken
into account I/O, magnetic shielding, cooling, and other
packaging issues will be required to expand the customer
base beyond a few specialty applications.
ACKNOWLEDGMENT
The authors would like to thank the NGST foundry team
for their many years of fabrication support, particularly in
establishing and maintaining stable fabrication processes,
and the NGST test and packaging teams for their many
years of timely support with parametric data, trend charting,
and wafer preparation. The authors would also like to thank
A. Kleinsasser and the e-beam lithography team at JPL for a
very successful collaboration, and F. D. Bedard of DoD and
D. Van Vechten of ONR for their continuing support of advanced
process development, and John Spargo, Andy Smith,
and Paul Bunyk of NGST and Professor Ted Van Duzer
of University of California, Berkeley for their valuable
discussions. We especially want to acknowledge the many
individuals who contributed to Table 1: K. K. Berggren,
Massachusetts Institute of Technology; F.-Im. Buchholz,
Physikalisch-Technische Bundesanstalt; W. Chen, State University
of New York, Stony Brook; P. Dresselhaus, National
Institute of Standards and Technology (NIST); M. Hidaka,
SRL; G. Hilton, NIST; Prof. W. Jutzi, Universität Karlsruhe;
X. Meng, University of California, Berkeley; H.-G. Meyer,
IPHT-Jena; A. Shoji, AIST; S. K. Tolpygo, HYPRES; and
J.-C. Villégier, CAE-Grenoble.
REFERENCES
[1] K. K. Likharev and V. K. Semenov, “RSFQ logic/memory family:
A new Josephson-junction technology for sub-terahertz-clock-frequency
digital systems,” IEEE Trans. Appl. Superconduct., vol. 1,
pp. 3–28, Mar. 1991.
[2] W. Chen, A. V. Rylyakov, V. Patel, J. E. Lukens, and K. K. Likharev,
“Rapid single flux quantum T-flip flop operating up to 770 GHz,”
IEEE Trans. Appl. Superconduct., vol. 9, pp. 3212–3215, June 1999.
[3] K. K. Likharev, “RSFQ: The fastest digital technology,” in Proc. 5th
Eur. Workshop Low Temperature Electronics 2002, p. 155.
[4] T. Sterling, “How to build a hypercomputer,” Sci. Amer., pp. 38–45,
July 2001.
[5] T. Sterling, G. Gao, K. K. Likharev, P. M. Kogge, and M. J. Mac-
Donald, “Steps to petaflops computing: A hybrid technology multithreaded
architecture,” in Proc. IEEE Aerospace Conf. 1997,vol.2,
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1530 PROCEEDINGS OF THE IEEE, VOL. 92, NO. 10, OCTOBER 2004