Superconducting Technology Assessment - nitrd

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Another issue is the cost of the refrigeration. Buildings and infrastructure may be a major cost factor for large amounts of refrigeration. Effort should be made to reduce the refrigeration at 4 K and at higher temperatures since the cost (infrastructure and ownership) is direct function of the amount of heat to be removed (Figure 11). Refridgerator Capital Cost in 1997 Dollars (M$) 100 10 1 .1 .01 .0001 Cost (M$) = 1.77 Refridgeration (kW)**0.7 .001 .01 Figure 11. The cost of various refrigerators as a function of the refrigeration. One key issue is the availability of manufacturers. The largest manufacturer of 4 K coolers is Sumitomo in Japan. Sumitomo has bought out all of its competitors except for Cryomech. There No American company has made large helium refrigerator or liquefier in the last 10 years, the industrial capacity to manufacture large helium plants having died with the <strong>Superconducting</strong>-Super-Collider in 1993. Development funding may be needed for U.S. companies to insure that reliable American coolers will be available in the future. Development toward a 10 W or larger 4 K cooler would be desirable to enable a supercomputer with a modular cryogenic unit. Power Distribution and Cables SFQ circuits are DC powered. Due to the low voltage (mV level), the amount of current to be supplied is in the range of few Amps for small scale systems and can be easily kiloAmps for large scale systems. Therefore, special precaution needs to be taken to provide DC power to the system. Large currents require low DC resistances that translate to large of amount of metal lines. However lower thermal conductance implies high resistance cables, since the thermal conductance of a metallic line is inversely proportional to the electrical resistance. High electrical resistance gives high Joule heating for dc bias lines and high attenuation for ac I/O lines. Therefore, each I/O design must be customized to find the right balance between thermal and electrical properties. Reliable cable attach for thousands of connection requires also cost efficient assembly procedures with high yield. .1 1 10 10 239
Supplying DC current to all of the SCE chips in parallel would result in a total current of many kiloAmperes. Several methods may be used to reduce this total current and heat load. One technique is to supply DC current to the SCE chips in series, rather than in parallel (current recycling) taking advantage of very low resistances of lines in SCE circuits. However, it would require true differential signal propagation across floating ground planes. High temperature superconductor (HTS) cables may be used to bring in DC current from 77 K to the 4 K environment. Another solution is to use switching power supplies: high voltages/low currents can be brought near SCE circuits and conversion to low voltages/high currents, all at DC, can occur at the point of use. However, this method employs high power field-effect transistor switches, which themselves can dissipate significant power. Of these methods, current recycling shows the most near-term promise. Laboratory level experiments were conducted for small scale systems. The demonstration of a large-scale SCE system with kiloAmperes of current was not performed yet. For smaller IO counts, coaxial cables can be used for both high and medium-speed lines. Coax cables have different sections. The middle section is a short length of stainless steel coaxial cable that has a high thermal resistance and a bottom section of non-magnetic Cu coaxial cable for penetration into the magnetically-shielded chip housing. For higher-frequency input signal up to 60 GHz and clock lines, Gilbert- Corning GPPO connectors are used. Flexible BeCu microstrip ribbon cables were also considered for medium speed output lines. At 1 GHz, electrical attenuation and heat conduction of these ribbon cables were measured to be nearly identical to the tri-section coax cable. Modified connector assemblies were tested at room temperature and at liquid nitrogen temperature and found to be within specification for both reflection and attenuation. For systems with hundreds or thousands of I/O lines, coaxial cables are not practical. To meet this challenge flexible ribbon cables have been developed 8 . These cables consist of two or three layers of copper metallization separated by dielectric films, typically polyimide. With three copper layers, the outer two layers serve as ground planes and the inner layer forms the signal lines, creating a stripline configuration. Stripline cables provide excellent shielding for the signal lines. The dielectric layers consisted of 2 mil thick polyimide films. The ground planes were fabricated from 0.6 micron-thick sputtered-copper films, while the signal lines were patterned from a 4-micron-thick plated-copper film. The signal line width was 3 mils for 50Ω impedance with a pitch of 70 mils and each cable has more than hundred leads. In addition to large I/O count and multi-GHz connections, flexible ribbon cables offer the advantage of low thermal conduction to the cold stage. Cables can be manufactured with copper films the thickness of the electrical skin depth for a particular frequency of interest. Successful cable-attach procedures with high reliability and low cost were also demonstrated. Signal speeds up to 3 GHz were experimentally demonstrated. The construction of the cable should allow operation up to 20GHz after minor modifications. Figure 12. A high-speed flexible ribbon cable designed for modular attachment (Ref: NGST). 8 “Cryogenic Packaging for Multi-GHz Electronics” T. Tighe et al, IEEE Tran. Applied Superconductivity, Vol 9 (2), pp3173-3176, 1999. 240 Interposer Board Heat stationed at cold pedestal Interposer Strip Substrate with traces connecting input and output lines LNA Board Heat stationed at 1st stage Interposer Board Interposer Strip Metal pads Dewar Wall Cable Indium bumps Breakout Board
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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Structurally, a high-end computer w
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16 ■ Chalmers University in Swede
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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MCMs The design of MCMs for SCE chi
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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Circuits/ Organizations Flux-1/ NG,
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3.1.2 RSFQ PROCESSORS - READINESS F
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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4.6 ROADMAP AND FACILITIES STRATEGY
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Figure 4-6. Timeline for developmen
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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98 Data Communication Requirement R
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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6.2. 3-D PACKAGING Conventional ele
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ Construct a detailed supercondu
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Appendix B
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140 George Cotter Nancy Welker Doc
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Appendix C
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144 TERMS/DEFINITIONS IHEC Integrat
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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0.08 0.06 0.04 0.02 30 40 50 60 70
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Appendix I
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Table 1 Representative Nb and NbN-B
Page 201 and 202: ground plane may be located either
Page 203 and 204: Fig. 4. Junction fabrication proces
Page 205 and 206: Table 6 Junction Array Summary of T
Page 207 and 208: Fig. 11. Ground plane planarization
Page 209 and 210: B. Yield Yield measurements are an
Page 211 and 212: Fig. 17. Photograph of the FLUX-1r1
Page 213 and 214: [47] B. Bumble, H. G. LeDuc, J. A.
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Page 217 and 218: Fig. 2. The Schematic View describe
Page 219 and 220: Fig. 4. The VHDL View captures the
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Page 227 and 228: 1. CURRENT STATUS OF OPTICAL INTERC
Page 229 and 230: 1.2. CURRENT OPTICAL INTERCONNECT R
Page 231 and 232: If technology, power, or cost limit
Page 233 and 234: 3.4 COARSE VS. DENSE WAVE DIVISION
Page 235 and 236: 3.5 DEVELOPMENTS FOR LOW TEMPERATUR
Page 237 and 238: 5. ROADMAP The roadmap below shows
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Page 241 and 242: The bandwidth, chip density and int
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Page 245 and 246: We must note that the reparability
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Page 251: Although cooling of the 4 K circuit
Page 255 and 256: These properties enable the possibi
Page 257: For additional copies, please conta
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