Superconducting Technology Assessment - nitrd

The panel has described an aggressive program to achieve yield, density, and performance of IC chips suitable for
petaflops-scale computing. As indicated in Table 4-10, the total estimated cost associated with IC chip manufacture
over a five-year program is $125.1M. A significantly reduced level of funding of roughly half of this figure could
enable the establishment only of pilot line capabilities with manufacturing yield low or unknown, and less-than-desired
IC chip densities. Clock rates would probably be increased to targets discussed in this study, as this is an area of
high research interest. However, the processes used to achieve the devices for 50 GHz and greater clock rates
would most likely use low-volume steps (e.g., e-beam lithography) and not be amenable to scaling for production.
It is estimated that current funding for superconductive-digital-IC chip manufacture, even at an R&D level, is far
less than $2M per year when both industrial and government funding are taken into account. At the current level
of spending on superconductive-digital-IC chip manufacturing, it is certain that chips of the density required for
petaflops-scale digital systems will not become available in the foreseeable future.
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