Superconducting Technology Assessment - nitrd

Different sections of a large chip, as well as different chips, may have to operate asynchronously at 50 to 100 GHz
clock frequencies and above. Clocks will have to be resynchronized at specific points in the circuit. Efficient methods
to resynchronize and re-clock SFQ signals have been demonstrated.
Clock frequencies of 50 to 100 GHz will be limited more by circuit microarchitecture, timing and jitter in timing,
and inter-gate delays, than by intra-gate delay. The inter-gate delay can be reduced by smaller gates placed closer
together. This will depend on both fabrication technology and size-efficient gate design. Timing jitter is reduced by
ballistic SFQ signal propagation between gates via matched passive transmission lines (PTL), rather than by active
transmission lines consisting of a string of SFQ pulse repeaters (referred to as a Josephson transmission line, JTL).
Since the junction impedance increases proportional to J C, higher J C enables narrower stripline/microstripline at the
same dielectric thickness, again increasing potential circuit density. Most improvement in both gate density and
clock frequency can be achieved by adding superconducting wiring layers as discussed above.
Jitter and timing errors and are probably the most insidious factors in reducing margins as the clock frequency
increases. Jitter occurs in all active devices: gates, fan-out and fan-in, and the clock distribution network. It is
caused by all noise sources that can modulate the switching time: thermal noise in resistors, external noise, noise
in the clock (particularly when externally supplied), and disturbs from clock and signal distribution. Jitter impacts
the margins of clocked gates more than asynchronous gates because clocked gates need to synchronize the arrival
of data and clock. It can reduce margins at high clock frequencies and therefore limit the useful clock frequency.
Circuits are frequently designed without careful consideration of these jitter/noise sources. Consequently, when
migrating to large circuits, margins could shrink rapidly.
Clock distribution is an important source of jitter if a large number of JTLs and splitters are used to propagate and
distribute the clock. Every stage contributes jitter that accumulates as square-root of the number of stages. The
use of PTLs instead of active JTLs will alleviate one source. However, splitters required to regenerate the clock
remain a major source of jitter. A multi-line clock from a coherent clock array could reduce this jitter. Nevertheless,
jitter will always be the ultimate limit on performance at high clock frequency.
Timing errors in design can be fatal and will occur if rigorous timing analysis is not part of the circuit design
methodology. Commercial tools such as VHDL are available, but have not been widely used. Because of jitter, precise
timing cannot be ensured. So, timing-error tolerant design should be used in critical circuits. Several methods to
ensure proper data/clock timing within a clock cycle that add minimal circuit overhead have been demonstrated.
Other Noise Sources
In addition to ubiquitous thermal noise, there is noise in all input/output lines, including power lines, which feed
back into the SFQ circuits. Noise measurements of circuits operating at 4 K almost universally show elevated noise
levels, with typical effective noise temperatures of ~40 K. The sources for such noise are magnetic field noise and
noise introduced by lines connected to warm noise sources. Even if testing is performed in a shielded environment,
every wire, cable, etc., from RT to 4 K serves as an antenna that pipes signals and noise into the 4 K circuit. It is
essentially impossible to provide a DC to infrared filter even in shielded rooms. Moreover, the terminations of RT test
equipment generate at least 300 K wideband noise. This needs to be filtered at low temperature, preferably at 4 K.
One way to avoid some of the “antenna” noise is for all digital data lines to have a digital “optical isolator” that
transmits only the desired bits and rejects all analog noise. Optical interconnects, under consideration for the
wideband data links, could provide this added benefit. Even if optical interconnects are not used for the RT to 4 K
data links, they should be considered as RFI isolators within the shielded cryostat environment at 300 K.
Power lines are particularly susceptible to transmitting various noise signals. Because of the high currents, filtering
at low temperature is more difficult. One concept is to bring power from RT to ~40 K as RF, filter the RF with a
narrow-band high temperature superconductor filter, and convert the RF to DC at 40 K. This has several
advantages, including power transmission at high voltage and low current to reduce ohmic heating and noise
filtering. From ~ 40 K, one can use zero-resistance high temperature superconductor current leads to 4 K.
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