Superconducting Technology Assessment - nitrd

Compact Package Feasible
Thousands to tens of thousands of SC processors and large amounts of memory will require significant levels of
cryogenic packaging. A compact system package is needed to support low latency requirements and to effectively use
available cooling techniques. The panel’s conclusions for supporting technologies were:
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■ Input/Output (I/O) circuits, cabling, and data communications from RSFQ to room
temperature electronics above 10 GHz, reliable multiple-temperature interfaces
and the design for larger applications have not been completely investigated.
■ Output interfaces are one of the most difficult challenges for superconductive electronics.
■ A focused program to provide the capability to output 50 Gbps from cold to warm
electronics must overcome technical challenges from the power dissipation of the
interface devices at the cryogenic end.
Packaging
The panel noted that:
■ The design of packaging technologies (e.g., boards, MCMs, 3-D packaging) and
interconnects (e.g., cables, connectors) for SCE chips is technically feasible and
fairly well understood.
■ A foundry for MCMs and boards using superconducting wiring is a major need.
■ The technology for the refrigeration plant needed to cool large systems—along
with the associated infrastructure—is in place today.
■ Tools and techniques for testing a large superconducting digital system have not
been fully addressed yet.
Optoelectronic Components at Low Temperature
An issue which must be thoroughly explored is how well room temperature optical components function in a cryogenic
environment, or whether specially designed components will be needed.
Low Power a Two-edged Sword
The low power of RSFQ presents a challenge for data output. There is not enough signal power in an SFQ data bit
to drive a signal directly to conventional semiconductor electronics; interface circuits are required to convert the
SFQ voltage pulse into a signal of sufficient power. While Josephson output circuits have been demonstrated at
data rates up to 10 Gbps, and there is a reasonable path forward to 50 Gbps output interfaces in an advanced
foundry process, a focused program is required to provide this capability.
Interconnection Network
The interconnection network at the core of a supercomputer is a high-bandwidth, low-latency switching fabric with
thousands or even tens of thousands of ports to accommodate processors, caches, memory elements, and storage
devices. The Bedard crossbar switch architecture, with low fanout requirements and replication of simple cells, is a
good candidate for this function.
Optical Switching Looks Promising
The challenges imposed by tens of Pbps between the cold and room temperature sections of a petaflops-scale
superconducting supercomputer require the development of novel architectures specifically designed to best suit
optical packet switching, which has the potential to address the shortcomings of electronic switching, especially in
the long term.