Superconducting Technology Assessment - nitrd

For system-in-stack purposes, it was necessary to develop a technique to be able to stack packaged components
and/or bare die components. This technique creates uniform size layers with non-uniform die sizes in each layer by
creating a frame around the die (or dice) using potting as shown in Figure 4. Process starts with a bumped KGD
encapsulated in a potting compound. Thin film metal traces contact the I/O bumps and route the signals to the
edges of the potting material. The layer is ground from the backside resulting in a thin (100-250 micron) complete
layer. The stack is created by laminating many layers with a cap substrate, which uses through-holes to provide I/O
paths. Metalization is applied on one or more sides to interconnect layers and the cap substrate.
System-in-stacks with heterogeneous mix of components and the needed discretes for the high-speed operation
of the stack can be realized. Multi-layer traces can be used to support complex interconnect structures needed for
multi-chip layers and for high-speed operation up to 30 GHz. Heat management layers (such as copper, diamond,
etc.) can be added on top of active components. These layers have dual functions:
■ Providing a low-resistance, direct path for efficient thermal flow to the edge of the stack
to keep the maximum temperature in the stack under control.
■ Serving as shims to maintain the total layer-to-layer tolerances of the stack for high-density
edge interconnect structures.
The manufacturability is maintained by allowing loose tolerances in the layer formation (component height variations,
substrate thickness variations). Heterogeneous 3D chip stacking is a versatile technology allowing stacking of
non-electronic components. Waveguides, vertical cavity surface emitting lasers, detectors are among devices used
in stack layers. The free surfaces of the stacks are especially suitable for these types of devices. Optical interconnects
from stack to stack and integrated focal plane arrays were already demonstrated 4 . Superconducting electronic
circuits based on NbN and Nb Josephson junctions were inserted in stack layers and operated at temperatures as
low as 4 K indicating the flexibility and reliability of the material system used in 3D chip stacks (Figure 5). Stacked
systems were operated at 20 GHz. There are proposed approaches to integrate MEMS devices and passive optical
components in stacks.
When the material selection and system design is judiciously performed, chip stacks have been shown to operate
reliably with MTTF exceeding 10 years, in a wide temperature range (from – 270 C to 165 C) and in hostile
environments subjected to 20,000 G. 3D packaging provides an excellent alternative to satisfy the needs high
functionality system and sub-system integration applications, yielding system architectures that cannot be
realized otherwise.
Thermal management is a key issue when aggressive miniaturization is used to pack large electronic functionalities
into small volumes. When the power budget increases, thermal management layers can be inserted in the stack as
alternating layers in addition to active layers. Experimental and analytical results indicated that up to 80W can be
dissipated in a stack volume of 1cm 3 . Thermal resistance within the stack can be as low as 0.1 C/W. Minimal
thermal resistance is critical for superconducting electronic applications where the components need to operate at 4 K.
Other trade-offs associated with 3D packaging are:
■ Cost.
■ Test.
■ Reparability.
4 V. Ozguz, P. Marchand, Y. Liu, Proc. International Conference on High Density Interconnect and System Packaging, (2000), p. 8
231