Hardware-Entwurf mit VHDL

Hardware-Entwurf mit VHDL
Prof. Dr.-Ing. Stefan Wolter Elektrotechnik und Informatik
Testbench für die Simulation eines AND3-Gatters:
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY tb_3pin IS
END tb_3pin;
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ARCHITECTURE arch_tb_3pin OF tb_3pin IS
SIGNAL a,b,c,r,y: std_logic;
COMPONENT mut_socket
PORT (a,b,c: IN std_logic;
END COMPONENT;
y : OUT std_logic);
FILE stimres : text OPEN read_mode IS "stimres";
FILE errors : text OPEN write_mode IS "errors";
BEGIN
model_under_test: mut_socket PORT MAP (a,b,c,y);
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-- Stimulis und Antworten aus der Datei stimres lesen
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read_stimuli_and_responses: PROCESS
VARIABLE Zeile : line;
VARIABLE read_ok: boolean;
VARIABLE Zeit : time;
VARIABLE Signalname : character;
VARIABLE space : character;
VARIABLE data : std_logic;
BEGIN
WHILE NOT endfile(stimres) LOOP
-- Lese Zeile
READLINE (stimres, Zeile);
VHDL - SIMULATION 108