Hardware-Entwurf mit VHDL

Hardware-Entwurf mit VHDL
Prof. Dr.-Ing. Stefan Wolter Elektrotechnik und Informatik
• Reservierte VHDL-Schlüsselwörter:
ABS FILE NULL SELECT
ACCESS FOR SEVERITY
AFTER FUNCTION OF SHARED *)
ALIAS ON SIGNAL
ALL GENERATE OPEN SLA *)
AND GENERIC OR SLL *)
ARCHITECTURE GROUP *) OTHERS SRA *)
ARRAY GUARDED OUT SRL *)
ASSERT SUBTYPE
ATTRIBUTE IF PACKAGE
IMPURE *) PORT THEN
BEGIN IN POSTPONED *) TO
BLOCK INERTIAL *) PROCEDURAL **) TRANSPORT
BODY INOUT PROCEDURE TYPE
BUFFER IS PROCESS
BUS PROTECTED **) UNAFFECTED *)
LABEL PURE *) UNITS
CASE LIBRARY UNTIL
COMPONENT LINKAGE RANGE USE
CONFIGURATION LITERAL *) RECORD
CONSTANT LOOP REFERENCE **) VARIABLE
REGISTER
DISCONNECT MAP REJECT*) WAIT
DOWNTO MOD REM WHEN
REPORT WHILE
ELSE NAND RETURN WITH
ELSIF NEW ROL *)
END NEST ROR *) XNOR *)
ENTITY NOR XOR
EXIT NOT
*) ab IEEE-Standard 1076-1993, **) ab IEEE-Standard 1076-2002
Tabelle 2.1: Reservierte VHDL-Schlüsselwörter
VHDL-GRUNDLAGEN 19