TI486 Microprocessor - Al Kossow's Bitsavers

Overview
Table 3-1. TI486SLCIE Signal Summary
SIGNAL SIGNAL NAME SIGNAL GROUP
A20M
Address bit 20 mask
A23-A1 Address bus lines Address bus
ADS Address strobe Bus cycle control
BHE Byte high enable Address bus
BLE Byte low enable Address bus
BUSY Processor extension busy Coprocessor interface
CLK2
D15-DO
2X clock input
Data bus lines
D/C Data/control Bus cycle definition
ERROR Processor extension error Coprocessor interface
FLT
Float
FLUSH Cache flush Internal cache interface
HLDA Hold acknowledge Bus arbitration
HOLD Hold request Bus arbitration
INTR Maskable interrupt request Interrupt control
KEN Cache enable Internal cache interface
LOCK Bus lock Bus cycle definition
M/IO Memory/input-output Bus cycle definition
NA Next address request Bus cycle control
NMI Non-maskable interrupt request Interrupt control
PEREQ Processor extension request Coprocessor interface
READY Bus ready Bus cycle control
RESET
Reset
SMADS SMM address strobe Bus cycle control
SMI System management interrupt Interrupt control
SUSP Suspend request Power management
SUSPA Suspend acknowledge Power management
W/R Write/read Bus cycle definition
The following sections describe the signals and their functional timing
characteristics. Additional signal information may be found in Chapter 5,
Electrical Specifications. Chapter 5 documents the dc and ac characteristics
for the signals including voltage levels, propagation delays, setup times, and
hold times. Specified setup and hold times must be met for proper operation
of the T1486.
3-5