TI486 Microprocessor - Al Kossow's Bitsavers

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Functional Timing Figure 4-9. Various Pipelined Cycles (One Wait State) CLK2 A31-A2, BE, BE, MilO, ole I ... I I T1P I Cycle 1 Pipelined --.14 (Write) I I T2P T2P I Cycle 2 Pipelined (Read) ~4 I I Cycle 3 Pipelined Cycle 4 Pipelined .-14 (Write) I (Read) I I T1P T2 T2P I T1P T21 T2P I T1P I I W/R I I I ADS is asserted as soon as the CPU has another bus cycle to perform, which is not always immediately after NA is asserted. r---+---~~~~ ADS I I I I I As long as the CPU enters the T2P state during Cycle 3, address pipelining is maintained in Cycle 4. I I J I I J J Asserting NA more than NA could have been asserted in I once during any cycle has I T1 P if desired. Assertion now is I no additional effects. I the latest time possible to allow I I the CPU to enter T2P state to I I I I maintain pipelining in Cycle 3. I I I I I I I ~I I WI I I : : iMtf : : I I 031-00 Out 1 >+- ......,.---..--.........-...,j I I Initiating and Maintaining Pipelined Cycles Pipelined addressing is always initiated by asserting NA during a non-pipelined bus cycle with at least one wait state. The first bus cycle following RESET, an idle bus, or a hold acknowledge state is always non-pipelined. Therefore, the TI486DLC/E always issues at least one non-pipelined bus cycle following RESET, idle, or hold acknowledge before pipelined addressing takes effect. 4-27
Functional Timing Once a bus cycle is in progress and the current address has been valid for one entire bus state, the NA input is sampled at the end of every phase one until the bus cycle is acknowledged. Once NA is sampled active, the TI486DLC/E microprocessor is free to drive a new address and bus cycle definition on the bus as early as the next bus state and as late as the last bus state in the cycle. Figure 4-10 illustrates the fastest transition possible to pipelined addressing following an idle bus state. In Cycle 1, NA is driven during state T2. Thus, Cycle 1 makes the transition to pipelined address timing, since it begins with T1 but ends with T2P. Because the address for Cycle 2 is available before Cycle 2 begins, Cycle 2 is called a pipelined bus cycle, and it begins with a T1 P state. Cycle 2 begins as soon as READY asserted terminates Cycle 1. Figure 4-10. Fastest Transition to Pipelined Address Following Idle Bus State Idle 1 1 .~ 1 1 T1 Cycle 1 Non-Pipelined (Write) Cycle 2 Pipelined 1 (Read) 1 --1 l1li --I~ T1P 1 T2P : Cycle 3 Pipelined 1 (Write) 1 ·I~ 1 1 1 T2P 1 T1P Cycle 4 Pipelined (Read) 1 Idle 1 .II1II CLK2 A31-A2 _ BE3-BEO, MIlO, Die Note: LOCK " : Valid 1, « « Vflid 2 « V+ 3 : Valid t ~ 1 1 1 1 1 1 1 1 1 1 1 1 031-00 -L--.L-{,..---O-ut-1---}-....l-~ < Out 3 )-....l--....l-~-_ I I i I ~ i I I I ~ Following any idle bus state (Ti) the address is always non-pipe lined and NA is sampled only during wait states. To start address pipelining after an idle state requires a non-pipelined cycle with at least one wait state (Cycle 1 above). The pipelined cycles (2,3, and 4 above) are shown with various numbers of wait states. Figure 4-11 illustrates transitioning to pipelined addressing during a burst of bus cycles. Cycle 2 makes the transition to pipelined addressing. Comparing Cycle 2 to Cycle 1 of Figure 3-10 illustrates that a transition cycle is the same whenever it occurs consisting of at least T1, T2 (NA is asserted at that time), and T2P (provided the TI486DLC/E microprocessor has an internal bus request already pending). T2P states are repeated if wait states are added to the cycle. Cycles 2, 3, and 4 in Figure 4-11 show that once address pipelining is achieved it can be maintained with two-state bus cycles consisting only of T1P and T2P. 4-28 Tl486DLCIE Bus Interface
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Page 122 and 123: Functional Timing Initiating and Ma
Page 124 and 125: Functional Timing Figure 3-12. Comp
Page 126 and 127: Functional Timing Figure 3-13. Inte
Page 128 and 129: Functional Timing Shutdown Indicati
Page 130 and 131: Functional Timing Figure 3-17. Pipe
Page 132 and 133: Functional Timing As shown in Figur
Page 134 and 135: Functional Timing Figure 3-19. Requ
Page 138 and 139: Functional Timing Figure 3-22. 8MI
Page 140 and 141: Functional Timing HALT Initiated Su
Page 142 and 143: Functional Timing 3.2.12 Float Figu
Page 144 and 145: TI486DLC/E Bus Interface 4-1
Page 146 and 147: Chapter 4 TI486DLC/E Bus Interface
Page 148 and 149: Overview Table 4-1. TI486DLCIE SIgn
Page 150 and 151: Overview Table 4-2. Terminal Functi
Page 156 and 157: Overview Table 4-6. Signal States D
Page 158 and 159: Overview 4.1.2 Power Management 4.1
Page 160 and 161: Functional Timing 4.2 Functional Ti
Page 162 and 163: Functional Timing The TI486DLC/E da
Page 164 and 165: Functional Timing Non-Pipelined Rea
Page 166 and 167: Functional Timing Initiating and Ma
Page 168 and 169: Functional Timing Figure 4-8. Faste
Page 172 and 173: Functional Timing Once a pipelined
Page 174 and 175: Functional Timing 4.2.3 Bus Cycles
Page 176 and 177: Functional Timing Pipelined Cycles
Page 178 and 179: Functional Timing LOCK is activated
Page 180 and 181: Functional Timing 4.2.6 Halt and Sh
Page 182 and 183: Functional Timing Figure 4-17. Pipe
Page 184 and 185: Functional Timing Figure 4-19. Non-
Page 186 and 187: Functional Timing The TI486DLC/E sa
Page 188 and 189: Functional Timing 4.2.9 Hold Acknow
Page 192 and 193: Functional Timing 4.2.10 Coprocesso
Page 194 and 195: Functional Timing 4.2.12 Power Mana
Page 196 and 197: Functional Timing Stopping the Inpu
Page 198 and 199: Electrical Specifications 5-1
Page 200 and 201: Chapter 5 Electrical Specifications
Page 202 and 203: ElectricalConnecnons It is recommen
Page 204 and 205: Recommended Operating Conditions 5.
Page 206 and 207: DC Electrical Characteristics Table
Page 208 and 209: AC Characteristics Figure 5-2. TI48
Page 210 and 211: AC Characteristics Table 5-9. AC Ch
Page 212 and 213: AC Characteristics Table 5-11. AC C
Page 214 and 215: ____ AC Characteristics 5.5.3 RESET
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Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
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Pin Assignments Table 6-1. TI486SLC
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Pin Assignments Figure 6-3. TI486DL
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Package Dimensions 6.2 Package Dime
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Thermal Characteristics 6.3 Thermal
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Instruction Set 7-1
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Chapter 7 Instruction Set This sect
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Instruction Fields 7.2 Instruction
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Instruction Fields 7.2.5 reg Field
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Instruction Fields Table 7-7. mod r
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Instruction Fields 7.2.11 sreg3 Fie
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Clock Count Summary 7.4 Clock Count
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--- --;.J -L 01 Table 7-17. Instruc
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I . ~ -.....J Table 7-17. Instructi
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Table 7-17. Instructions, Opcodes,
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-....J N (J.) Table 7-17. Instructi
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I I i I i Table 7-17. Instructions,
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...... ...... '" Table 7-17. Instru
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-....J N co Table 7-17. Instruction
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"-.I ~ Table 7-17. Instructions, Op
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U Appendix A TI486 SMM Pro rammer's
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SMM Implementation A.2 SMM Implemen
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Figure A-1. SMM Memory Space Header
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SMM Implementation 6) NMI is the on
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Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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i**********************************
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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