TI486 Microprocessor - Al Kossow's Bitsavers

Overview
Table 3-2. Terminal Functions (Continued)
NAME
PIN
NO.
1/0 DESCRIPTION
BUSY 34 I Coprocessor Busy (active low). This is an input from the coprocessor that indicates to
the TI486SLC/E that the coprocessor is currently executing an instruction and is not yet
able to accept another opcode. When the TI486SLC/E processor encounters a WAIT
instruction or any coprocessor instruction that operates on the coprocessor stack (Le.,
load, pop, arithmetic operation), BUSY is sampled. BUSY is continually sampled and
must be recognized as inactive before the CPU will supply the coprocessor with another
instruction. However, the following coprocessor instructions are allowed to execute even
if BUSY is active since these instructions are used for coprocessor initialization and
exception clearing: FNINIT, FNCLEX.
BUSY is internally connected to a pullup resistor to prevent it from floating active when
left unconnected.
CLK2 15 I 2X Clock Input (active high). This signal is the basic timing reference for the
TI486SLC/E microprocessor. The CLK2 input is internally divided by two to generate the
internal processor clock. The external CLK2 is synchronized to a known phase of the
internal processor clock by the falling edge of the RESET signal. External timing
parameters are defined with respect to the rising edge of CLK2.
00 1
01 100
02 99
03 96
04 95
05 94
06 93
07 92
08 90
09 89
010 88
011 87
012 86
013 83
014 82
015 81
I/OIZ
Data Bus (active high). The Oata Bus (015-00) signals are 3-state bidirectional signals
that provide the data path between the TI486SLC/E and external memory and 1/0
devices. The data bus inputs data during memory read, 1/0 read and interrupt
acknowledge cycles and outputs data during memory and 1/0 write cycles. Oata read
operations require that specified data setup and hold times be met for correct operation.
The data bus signals are high active and float while the CPU is in a hold acknowledge
or float state.
O/C 24 OIZ Data/Control. This signal is low during control cycles and is high during data cycles.
Control cycles are issued during functions such as a halt instruction, interrupt servicing
and code fetching. Oata bus cycles include data access from either memory or 1/0.
ERROR 36 I Coprocessor Error (active low). This is an input used to indicate that the coprocessor
generated an error during execution of a coprocessor instruction. ERROR is sampled by
the TI486SLC/E processor whenever a coprocessor instruction is executed. If ERROR
is sampled active, the processor generates exception 16 which is then serviced by the
exception handling software.
Certain coprocessor instructions do not generate an exception 16 even if ERROR is
active. These instructions, which involve clearing coprocessor error flags and saving the
coprocessor state, are listed as follows: FNINIT, FNCLEX, FNSTSW, FNSTCW,
FNSTENV, FNSAVE. ERROR is internally connected to a pullup resistor to prevent it
from floating active when left unconnected.
ERROR is internally connected to a pullup resistor to prevent it from floating active when
left unconnected.
FLT 28 I Float (active low). This input forces all bidirectional and output signals to a 3-state
condition. Floating the signals allows the TI486SLC/E signals to be externally driven
without physically removing the device from the circuit. The TI486SLC/E CPU must be
reset following assertion or deassertion of FL T. It is recommended that FL T be used only
for test purposes.
FLT is internally connected to a pullup resistor to prevent it from floating active when left
unconnected.
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