TI486 Microprocessor - Al Kossow's Bitsavers

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Tl486SLCIE Overview Figure 1-2. TI486SLCIE Logic Symbol cI> MICROPROCESSOR TI486SLC/E CLK2 RESET 2x Clock Input Reset Bus Arbitration I Hold Request Hold Ack. .... ~ H OLD H LOA NM I INTR SM I ...... ........ Non-Maskable Req. Bus Ready 1..--1 -.....- ... Interrupt Maskable Req. Control 1..--1 .... Bus Next Address Req. ....- ~ ~ System Mgmt Int. Cycle Control Address Strobe \1 " R EADY A N OS A ~ ~ Float SMM Address Strobe \1 t--.. S MADS ~ Q Cache Enable Iiniernal Cache h ~ Cache Flush Interface PEREQ BUS Y ERRO R h b Data/Control \1 ~ Extension Req. Bus Memory I/O \1 ~ Extension Busy Coprocessor Interface Cycle Definition Write/Read \1 ~ Extension Error Bus Lock t--.. Die M/IO wif:t LOCK P A .b. Q Suspend Req., Power t--.. I Byte High En. 'V L Suspend Ack. Management Byte Enables Byte Low En. \1 '" M '" ~ Address Bit 20 Mask ~ I DO • o 15 0 1 \1< Data) I AddreS~\1 • • 15 23 A1 • A23 tThis symbol is in accordance with ANSI/IEEE Std 91-1984. 1-7
TI486SLCIE Overview The TI486SLC/E includes two power management signals (SUSP and SUSPA), two cache interface signals (FLUSH and KEN), an A20 mask input (A20M), and two SMM signals (SMADS and SMI) that are additions to the 386SX signal set. The complete list of TI486SLC/E signals is shown in Figure 1-3. Figure 1-3. TI486SLCIE Input and Output Signals A20M ----. • BUSY ----. CLK2 ----. ERROR ----. FLT ----. FLUSH ----. • INTR ----. HOLD ----. TI486SLC/E Microprocessor A23-A1 ADS BHE BLE D15-DO Die HLDA LOCK KEN ----. • NA ----. NMI----' PEREQ ----. SDSP ----. • READY ----. RESET ----. • MilO SOSPA SMADS 8MI W/R • Internal Cache Interface • Power Management • A20 Mask • System Management Mode 1-8 Product Overview
Page 1 and 2: .TEXAS INSTRUMENTS TI486 Microproce
Page 4 and 5: TI486 Microprocessor Reference Guid
Page 6 and 7: Preface Read This First About This
Page 8 and 9: About This Manual Appendix D Orderi
Page 10 and 11: Contents 1 Product Overview .......
Page 12 and 13: Contents 5.5 AC Characteristics . .
Page 14 and 15: 1-1 TI486SLC/E Functional Block Dia
Page 16 and 17: Figures 4-27 SUSP Initiated Suspend
Page 18 and 19: Tables 5-3 Absolute Maximum Ratings
Page 20 and 21: Product Overview 1-1
Page 22 and 23: Chapter 1 Product Overview Features
Page 24 and 25: 1.2 Differences Between the TI486SL
Page 28 and 29: Tl486DLCIE Overview 1.4 TI486DLC/E
Page 30 and 31: TI486DLCIE Overview The TI486DLC/E
Page 32 and 33: Power Management / System Managemen
Page 34 and 35: Programming Interface 2-1
Page 36 and 37: Chapter 2 In this chapter, the inte
Page 38 and 39: Processor Initialization Table 2-1.
Page 40 and 41: Instruction Set Overview 2.2 Instru
Page 42 and 43: Register Set 2.3 Register Set There
Page 44 and 45: Register Set Pointer and Index Regi
Page 46 and 47: Register Set 2.3.1.2 Segment Regist
Page 48 and 49: Register Set 2.3.1.3 Instruction Po
Page 50 and 51: Register Set 2.3.2 System Register
Page 52 and 53: Register Set 2.3.2.1 Control Regist
Page 54 and 55: Register Set 2.3.2.2 Descriptor Tab
Page 56 and 57: Register Set Table 2-6. Segment Des
Page 58 and 59: Register Set During task switching,
Page 60 and 61: Register Set The CCRO register (Tab
Page 62 and 63: Register Set Table 2-9. TI486DLCIE
Page 64 and 65: Register Set Table 2-12. ARR 1-ARR4
Page 66 and 67: Register Set 2.3.2.6 Test Registers
Page 68 and 69: Register Set Table 2-14. TR6 and TR
Page 70 and 71: Address Spaces 2.4 Address Spaces T
Page 72 and 73: Address Spaces 2.4.2 Memory Address
Page 74 and 75: Address Spaces Figure 2-21. Real Mo
Page 76 and 77:
Address Spaces Figure 2-24. Paging
Page 78 and 79:
Interrupts and Exceptions 2.5 Inter
Page 80 and 81:
Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
Page 86 and 87:
System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Page 106 and 107:
Page 108 and 109:
Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Page 138 and 139:
Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Page 192 and 193:
Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
Page 200 and 201:
Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
Page 206 and 207:
DC Electrical Characteristics Table
Page 208 and 209:
AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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Page 218 and 219:
Page 220 and 221:
Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
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Pin Assignments Table 6-1. TI486SLC
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Pin Assignments Figure 6-3. TI486DL
Page 228 and 229:
Package Dimensions 6.2 Package Dime
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Thermal Characteristics 6.3 Thermal
Page 232 and 233:
Instruction Set 7-1
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Chapter 7 Instruction Set This sect
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Instruction Fields 7.2 Instruction
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Instruction Fields 7.2.5 reg Field
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Instruction Fields Table 7-7. mod r
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Instruction Fields 7.2.11 sreg3 Fie
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Clock Count Summary 7.4 Clock Count
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--- --;.J -L 01 Table 7-17. Instruc
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I . ~ -.....J Table 7-17. Instructi
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Table 7-17. Instructions, Opcodes,
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Page 254 and 255:
-....J N (J.) Table 7-17. Instructi
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I I i I i Table 7-17. Instructions,
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...... ...... '" Table 7-17. Instru
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-....J N co Table 7-17. Instruction
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"-.I ~ Table 7-17. Instructions, Op
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U Appendix A TI486 SMM Pro rammer's
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SMM Implementation A.2 SMM Implemen
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Figure A-1. SMM Memory Space Header
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SMM Implementation 6) NMI is the on
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Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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i**********************************
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
Page 322:
~TEXAS INSTRUMENTS Printed in U.S.A
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