TI486 Microprocessor - Al Kossow's Bitsavers

Register Set
The CCRO register (Table 2-10) defines the type of cache and determines if
the 64-KByte memory area on 1-MByte boundaries and the 640-KByte to
1-MByte area are cacheable. This register also enables certain pins
associated with cache control and suspend mode.
The CCR 1 register (Table 2-11) is used to set up internal cache operation and
System Management Mode (SMM). The ARR registers (Figure 2-13,
Figure 2-14, and Table 2-8, Table 2-9) are used to define the location and
size of the memory regions associated with the internal cache. ARR1-ARR3
define three write-protected or non-cacheable memory regions as designated
by CCR1 bits WP1-WP3. ARR4 defines an SMM memory space or
non-cacheable memory region as defined by CCR1 bit SM4. Other CCR1 bits
enable RPL and SMM pins and control SMM memory access. The SMAC bit
allows access to defined SMM space while not in an SMI service routine. The
MMA bit allows access to main memory that overlaps with SMM memory while
in an SMI service routine for data access only.
The ARR registers define address regions using a starting address and a block
size. The non-cacheable region block sizes range from 4 KBytes to 4 GBytes
(Table 2-12). A block size of zero disables the address region. The starting
address of the address region must be on a block size boundary. For example,
a 128 KByte block is allowed to have a starting address of 0 KBytes,
128 KBytes, 256 KBytes, etc. The SMM memory region size is restricted to a
maximum of 16 MBytes. The block size must be defined for SMI to be
recognized.
2-27