TI486 Microprocessor - Al Kossow's Bitsavers

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1-1 TI486SLC/E Functional Block Diagram .......................................... , 1-6 1-2 TI486SLC/E Logic Symbol ..................................................... 1-7 1-3 TI486SLC/E Input and Output Signals ........................................... 1-8 1-4 TI486DLC/E Functional Block Diagram .......................................... 1-9 1-5 TI486DLC/E Logic Symbol .................................................... 1-10 1-6 TI486DLC/E Input and Output Signals .......................................... 1-11 2-1 Application Register Set ...................................................... 2-10 2-2 General Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-12 2-3 Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-14 2-4 EFLAGS Register ............................. '" ... , ............ , ............ 2-15 2-5 System Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-18 2-6 Control Registers ............................................................ 2-19 2-7 Descriptor Table Registers .................................................... 2-21 2-8 Application and System Segment Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-22 2-9 Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-24 2-10 Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-24 2-11 32-Bit Task State Segment (TSS) Table .................................. . . . . . .. 2-25 2-12 16-Bit Task State Segment (TSS) Table ......................................... 2-26 2-13 TI486SLC/E Address Region Registers (ARR1-ARR4) ........................... 2-28 2-14 TI486DLC/E Address Region Registers (ARR1-ARR4) ........................... 2-29 2-15 TI486SLC/E Debug Registers ................................................. 2-31 2-16 TI486DLC/E Debug Registers ................................................. 2-32 2-17 Test Registers ............................................................... 2-34 2-18 TI486SLC/E Memory and 1/0 Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-37 2-19 TI486DLC/E Memory and 1/0 Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-38 2-20 Offset Address Calculation .................................................... 2-40 2-21 Real Mode Address Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-41 2-22 Protected Mode Address Calculation ........................................... 2-41 2-23 Selector Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-42 2-24 Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-43 2-25 Directory and Page Table Entry (DTE and PTE) Format .................... . . . . . .. 2-43 2-26 Error Code Format ........................................................... 2-50 2-27 TI486SLC/E Memory and 1/0 Address Spaces .......... , ........... , ...... , ..... 2-51 2-28 TI486DLC/E Memory and 1/0 Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-52 2-29 SMM Execution Flow Diagram ................................................. 2-53 2-30 SMM Memory Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-54 2-31 SMM and Suspended Mode Flow Diagram ...................................... 2-57 3-1 TI486SLC/E Functional Signal Groupings ........................................ 3-4 3-2 Internal Processor Clock Synchronization ....................................... 3-16 3-3 Bus Activity from RESET until First Code Fetch .................................. 3-17 xiii
Figures 3-4 Fastest Non-Pipelined Read Cycles ............................................ 3-19 3-5 Various Non-Pipelined Bus Cycles (No Wait States) .............................. 3-20 3-6 Various Non-Pipelined Bus Cycles with Different Numbers of Wait States. . . . . . . . . . .. 3-21 3-7 Non-Pipelined Bus States ..................................................... 3-22 3-8 Fastest Pipelined Read Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-24 3-9 Various Pipelined Cycles (One Wait State) ...................................... 3-26 3-10 Fastest Transition to Pipelined Address Following Idle Bus State ................... 3-27 3-11 Transitioning to Pipelined Address During Burst of Bus Cycles ..................... 3-28 3-12 Complete Bus States ......................................................... 3-29 3-13 Interrupt Acknowledge Cycles ................................................. 3-31 3-14 Non-Pipelined Halt Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-32 3-15 Pipelined Shutdown Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-33 3-16 Non-Pipelined Cache Fills Using KEN (With Different Numbers of Wait States) ....... 3-34 3-17 Pipelined Cache Fills Using KEN (With Different Numbers of Wait States) ........... 3-35 3-18 Masking A20 Using A20M During Burst of Bus Cycles ............................ 3-37 3-19 Requesting Hold from Idle Bus State ........................................... 3-39 3-20 Requesting Hold from Active Non-Pipelined Bus ................................. 3-40 3-21 Requesting Hold f,rom Active Pipelined Bus ...................................... 3-41 3-22 SMI Timing .................................................................. 3-43 3-23 liD Trap Timing .............................................................. 3-43 3-24 SUSP Initiated Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-44 3-25 Halt Initiated Suspend Mode ....... , ..................... , ..................... 3-45 3-26 Stopping CLK2 During Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-46 3-27 Entering and Exiting Float ..................................................... 3-47 4-1 TI486DLC/E Functional Signal Groupings ... " ....... , .. " ., .................... , 4-4 4-2 Internal Processor Clock Synchronization ....................................... 4-17 4-3 Bus Activity from RESET until First Code Fetch .................................. 4-18 4-4 Fastest Non-Pipelined Read Cycles ............................................ 4-20 4-5 Various Non-Pipelined Bus Cycles (No Wait States) .............................. 4-21 4-6 Various Non-Pipelined Bus Cycles with Different Numbers of Wait States. . . . . . . . . . .. 4-22 4-7 Non-Pipelined Bus States .... " .... " ........... , ..... " ... '" ... , ...... " .... 4-23 4-8 Fastest Pipelined Read Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-25 4-9 Various Pipelined Cycles (One Wait State) ...................................... 4-27 4-10 Fastest Transition to Pipelined Address Following Idle Bus State ................... 4-28 4-11 Transitioning to Pipelined Address During Burst of Bus Cycles ..................... 4-29 4-12 Complete Bus States ......................................................... 4-30 4-13 Non-Pipelined Bus Cycles Using BS 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-32 4-14 Pipelining and BS 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-34 4-15 Interrupt Acknowledge Cycles ................................................. 4-35 4-16 Non-Pipelined Halt Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-37 4-17 Pipelined Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-39 4-18 Non-Pipelined Cache Fills Using KEN .......................................... 4-40 4-19 Non-Pipelined Cache Fills Using KEN and BS16 ................................. 4-41 4-20 Pipelined Cache Fills Using KEN .............................................. , 4-42 4-21 Masking A20 Using A20M During Burst of Bus Cycles ............................ 4-44 4-22 Requesting Hold from Idle Bus State ........................................... 4-46 4-23 Requesting Hold from Active Non-Pipelined Bus ................................. 4-47 4-24 Requesting Hold from Active Pipelined Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-48 4-25 SMI Timing .................................................................. 4-50 4-26 liD Trap Timing .............................................................. 4-50 xiv
Page 1 and 2: .TEXAS INSTRUMENTS TI486 Microproce
Page 4 and 5: TI486 Microprocessor Reference Guid
Page 6 and 7: Preface Read This First About This
Page 8 and 9: About This Manual Appendix D Orderi
Page 10 and 11: Contents 1 Product Overview .......
Page 12 and 13: Contents 5.5 AC Characteristics . .
Page 16 and 17: Figures 4-27 SUSP Initiated Suspend
Page 18 and 19: Tables 5-3 Absolute Maximum Ratings
Page 20 and 21: Product Overview 1-1
Page 22 and 23: Chapter 1 Product Overview Features
Page 24 and 25: 1.2 Differences Between the TI486SL
Page 26 and 27: Tl486SLCIE Overview Figure 1-2. TI4
Page 28 and 29: Tl486DLCIE Overview 1.4 TI486DLC/E
Page 30 and 31: TI486DLCIE Overview The TI486DLC/E
Page 32 and 33: Power Management / System Managemen
Page 34 and 35: Programming Interface 2-1
Page 36 and 37: Chapter 2 In this chapter, the inte
Page 38 and 39: Processor Initialization Table 2-1.
Page 40 and 41: Instruction Set Overview 2.2 Instru
Page 42 and 43: Register Set 2.3 Register Set There
Page 44 and 45: Register Set Pointer and Index Regi
Page 46 and 47: Register Set 2.3.1.2 Segment Regist
Page 48 and 49: Register Set 2.3.1.3 Instruction Po
Page 50 and 51: Register Set 2.3.2 System Register
Page 52 and 53: Register Set 2.3.2.1 Control Regist
Page 54 and 55: Register Set 2.3.2.2 Descriptor Tab
Page 56 and 57: Register Set Table 2-6. Segment Des
Page 58 and 59: Register Set During task switching,
Page 60 and 61: Register Set The CCRO register (Tab
Page 62 and 63: Register Set Table 2-9. TI486DLCIE
Page 64 and 65:
Register Set Table 2-12. ARR 1-ARR4
Page 66 and 67:
Register Set 2.3.2.6 Test Registers
Page 68 and 69:
Register Set Table 2-14. TR6 and TR
Page 70 and 71:
Address Spaces 2.4 Address Spaces T
Page 72 and 73:
Address Spaces 2.4.2 Memory Address
Page 74 and 75:
Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
Page 78 and 79:
Interrupts and Exceptions 2.5 Inter
Page 80 and 81:
Interrupts and Exceptions 2.5.3 Int
Page 82 and 83:
Interrupts and Exceptions Table 2-2
Page 84 and 85:
System Management Mode 2.6 System M
Page 86 and 87:
System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
Page 98 and 99:
Chapter 3 TI486SLC/E Bus Interface
Page 100 and 101:
Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Page 106 and 107:
Page 108 and 109:
Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
Page 112 and 113:
Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Page 138 and 139:
Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
Page 146 and 147:
Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Page 192 and 193:
Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
Page 198 and 199:
Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
Page 202 and 203:
ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
Page 206 and 207:
DC Electrical Characteristics Table
Page 208 and 209:
AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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Page 218 and 219:
Page 220 and 221:
Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
Page 224 and 225:
Pin Assignments Table 6-1. TI486SLC
Page 226 and 227:
Pin Assignments Figure 6-3. TI486DL
Page 228 and 229:
Package Dimensions 6.2 Package Dime
Page 230 and 231:
Thermal Characteristics 6.3 Thermal
Page 232 and 233:
Instruction Set 7-1
Page 234 and 235:
Chapter 7 Instruction Set This sect
Page 236 and 237:
Instruction Fields 7.2 Instruction
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Instruction Fields 7.2.5 reg Field
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Instruction Fields Table 7-7. mod r
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Instruction Fields 7.2.11 sreg3 Fie
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Clock Count Summary 7.4 Clock Count
Page 246 and 247:
--- --;.J -L 01 Table 7-17. Instruc
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I . ~ -.....J Table 7-17. Instructi
Page 250 and 251:
Table 7-17. Instructions, Opcodes,
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Page 254 and 255:
-....J N (J.) Table 7-17. Instructi
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I I i I i Table 7-17. Instructions,
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...... ...... '" Table 7-17. Instru
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-....J N co Table 7-17. Instruction
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"-.I ~ Table 7-17. Instructions, Op
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Page 266 and 267:
U Appendix A TI486 SMM Pro rammer's
Page 268 and 269:
SMM Implementation A.2 SMM Implemen
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Figure A-1. SMM Memory Space Header
Page 272 and 273:
SMM Implementation 6) NMI is the on
Page 274 and 275:
Instruction Summary A.4 Instruction
Page 276 and 277:
Instruction Summary A.4.3 Resume No
Page 278 and 279:
Instruction Summary A.4.6 Save LDTR
Page 280 and 281:
8MI Handler Example A.5 SMI Handler
Page 282 and 283:
8MI Handler Example execute_halt: C
Page 284 and 285:
8MI Handler Example COMMENT A The T
Page 286 and 287:
8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
Page 290 and 291:
Testing/Debugging SMM Code sgdt COM
Page 292 and 293:
Testing/Debugging SMM Code i*******
Page 294 and 295:
TI486 Power Management Features A.7
Page 296 and 297:
Detection of Tl486 CPU A.9 Detectio
Page 298 and 299:
Detection of SMM Capable Version A.
Page 300 and 301:
i**********************************
Page 302 and 303:
A.11 SMM Feature Comparison SMM Fea
Page 304 and 305:
SMM Instruction Macros COMMENT A Co
Page 306 and 307:
SMM Instruction Macros SMM Instruct
Page 308 and 309:
A.14 Format of Data Used by SVDC/RS
Page 310 and 311:
Altering SMM Code Limits A.1S Alter
Page 312 and 313:
SMM Errata A.16 SMM Errata The foll
Page 314 and 315:
Appendix B TI486 Cache Flush B.1 Ge
Page 316 and 317:
Appendix C TI486 BIOS Modification
Page 318 and 319:
Introduction Some example assembler
Page 320 and 321:
Appendix D Ordering Information 0.1
Page 322:
~TEXAS INSTRUMENTS Printed in U.S.A
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