TI486 Microprocessor - Al Kossow's Bitsavers

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Figure A-1. SMM Memory Space Header Top of SMM ---. Address Space Table A-1. SMM Memory Space Header SMM Implementation registers. The INT 3 debug code trap technique can be used, however, prior to the occurrence of the 8MI in 8MM space. Once the 8MI has occurred and the debugger has control in 8MM space, the debug registers can be used for the remaining 8MI execution. 31 o 31 31 DR7 -4h EFLAGS -8h CRO -Ch Current IP -10h Next IP 16 15 0 -14h Reserved CS Selector I -18h CS Descriptor (Bits 63-32) -1Ch CS qescriptor (Bits 31-0) 2 1 0 -20h Reserved Ipl'l -24h Reserved -28h Reserved -2Ch ESI or EDI -30h NAME DESCRIPTION DR? The contents of the debug register? EFLAGS The contents of the extended flag register. CRO The contents of the control register O. Current IP The address of the instruction executed prior to servicing the SMI interrupt. Next IP The address of the next instruction that will be executed after exiting the SMM mode. CS Selector Code segment register selector for the current code segment. CS Descriptor Code register descriptor for the current code segment. P I ESI or EDI REP INSxlOUTSx Indicator P = 1 if current instruction has a REP prefix P = 0 if current instruction does not have REP prefix IN, INSx, OUT, or OUTSx Indicator I = 1 if current instruction performed is an I/O WRITE I = 0 if current instruction performed is an I/O READ Restored ESI or EDI value. Used when it is necessary to repeat an REP OUTSx or REP INSx instruction when one of the I/O cycles caused an SMI trap SIZE 4 Bytes 4 Bytes 4 Bytes 4 Bytes 4 Bytes 2 Bytes 8 Bytes 1 Bit 1 Bit 4 Bytes Note: Note: INSx = INS, INSB, INSW, or INSD instruction. OUTSx = OUTS, OUTSB, OUTSW, or OUTSD instruction. A.2.2.2 Exiting the SMI Handler When the R8M instruction is executed at the end of the 8MI handler the IP is loaded from the top of the 8MM at the address (8MMbase +8MMsize - 14h) called 8M,-NEXTIP. This permits the instruction to be restarted. The values A-5
SMM Implementation of ECX, ESI, and EDI, prior to the execution of the instruction that was interrupted by SMI, can be restored from information in the header that pertains to the INx and OUTx instructions. The only registers that are restored from the 8MM header are CS, N EXT_I P, EFLAGS, CRO, and DR7. A.2.2.3 Addressing SMM Code With the Same Address as Main Memory MMAC = shl 3 mov aI, out 22h, in mov mov aI, ah, aI, out 22h, mov or aI, aI, out 23h, To access main memory overlapping the SMM space (Le., generate ADS from memory MOV instructions rather than SMADS) set the MMAC bit in CCR1. The following code will enable MMAC: Oclh al 23h al Oclh al ah MMAC al iselect CCRl iget CCRl current value isave it iset MMAC iNow all data memory access will use ADS#, Code fetches will continue to be done i with SMADS# from SMM memory iDisable MMAC mov aI, Oclh iselect CCRl out 22h, al mov aI, ah iget old value of CCRl out 23h, al iand restore it A.2.2.4 Miscellaneous Execution Details 1) Execution of SMM code begins at the start of SMM space. This is the value entered onto the base portion of AAR4. The C8 base will be set to the ARR4 SMM base, and EIP will be equal to O. 2) The A20 input to the CPU is ignored for all SMM space accesses. These are all accesses which use 8MADS. 3) <strong>Al</strong>l SMM instructions can be executed outside the SMM defined space, provided that 8MAC bit is set in CCR1 or if execution of an SMI handler is in progress. (An 8MI handler is "in progress" during the time the CPU is driving the SMI pin low.) 4) Setting the MMAC bit permits the reading and writing of main memory addresses that overlaps 8MM memory while an 8MI is in progress. 5) It is not possible to execute code in main memory that overlaps SMM memory addresses. A-6 Tl486 SMM Programmer's Guide
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
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DC Electrical Characteristics Table
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AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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Page 220 and 221: Mechanical Specifications 6-1
Page 222 and 223: Chapter 6 Mechanical Specifications
Page 224 and 225: Pin Assignments Table 6-1. TI486SLC
Page 226 and 227: Pin Assignments Figure 6-3. TI486DL
Page 228 and 229: Package Dimensions 6.2 Package Dime
Page 230 and 231: Thermal Characteristics 6.3 Thermal
Page 232 and 233: Instruction Set 7-1
Page 234 and 235: Chapter 7 Instruction Set This sect
Page 236 and 237: Instruction Fields 7.2 Instruction
Page 238 and 239: Instruction Fields 7.2.5 reg Field
Page 240 and 241: Instruction Fields Table 7-7. mod r
Page 242 and 243: Instruction Fields 7.2.11 sreg3 Fie
Page 244 and 245: Clock Count Summary 7.4 Clock Count
Page 246 and 247: --- --;.J -L 01 Table 7-17. Instruc
Page 248 and 249: I . ~ -.....J Table 7-17. Instructi
Page 250 and 251: Table 7-17. Instructions, Opcodes,
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Page 260 and 261: -....J N co Table 7-17. Instruction
Page 262 and 263: "-.I ~ Table 7-17. Instructions, Op
Page 266 and 267: U Appendix A TI486 SMM Pro rammer's
Page 268 and 269: SMM Implementation A.2 SMM Implemen
Page 272 and 273: SMM Implementation 6) NMI is the on
Page 274 and 275: Instruction Summary A.4 Instruction
Page 276 and 277: Instruction Summary A.4.3 Resume No
Page 278 and 279: Instruction Summary A.4.6 Save LDTR
Page 280 and 281: 8MI Handler Example A.5 SMI Handler
Page 282 and 283: 8MI Handler Example execute_halt: C
Page 284 and 285: 8MI Handler Example COMMENT A The T
Page 286 and 287: 8MI Handler Example arrl arr2 arr3
Page 288 and 289: .MODEL SMALL . STACK .386P INCLUDE
Page 290 and 291: Testing/Debugging SMM Code sgdt COM
Page 292 and 293: Testing/Debugging SMM Code i*******
Page 294 and 295: TI486 Power Management Features A.7
Page 296 and 297: Detection of Tl486 CPU A.9 Detectio
Page 298 and 299: Detection of SMM Capable Version A.
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Page 302 and 303: A.11 SMM Feature Comparison SMM Fea
Page 304 and 305: SMM Instruction Macros COMMENT A Co
Page 306 and 307: SMM Instruction Macros SMM Instruct
Page 308 and 309: A.14 Format of Data Used by SVDC/RS
Page 310 and 311: Altering SMM Code Limits A.1S Alter
Page 312 and 313: SMM Errata A.16 SMM Errata The foll
Page 314 and 315: Appendix B TI486 Cache Flush B.1 Ge
Page 316 and 317: Appendix C TI486 BIOS Modification
Page 318 and 319: Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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