TI486 Microprocessor - Al Kossow's Bitsavers

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Functional Timing Figure 3-3. Bus Activity from RESET until First Code Fetch ClK2 r.---- Reset -----II.~I~..---- Internal .1 Cycle 1 Initialization Non-Plpehned ;:=: 15ClK2 duration if not I 12 going to request self-test. ( If self-test is performed, add II (Read) I ;:=: 80 ClK2 duration before ~ 20 requsting self-test. I 20 + 60* to these numbers T1 T2 3m~' RESET ClK --v-V-v-v-v-1. (lnternal)~ * Approximately \~----------------~I----~I - 121 11 21 112 1 2 11121 ~i1J1\... BUSY ~\ High for no Se~-Test (see Note) \~~ ~ low to Begin Self Test ~ I I Note: BUSY should be held stable for 80 ClK2 periods before and after the ClK2 period in which RESET falling edge occurs. 3.2.2 Bus Operation The TI486SLC/E microprocessor communicates with the external system through separate, parallel buses for data and address. This is commonly called a demultiplexed address/data bus. This demultiplexed bus eliminates the need for address latches required in multiplexed address/data bus configurations where the address and data are presented on the same pins at different times. TI486SLC/E instructions can act on memory data operands consisting of 8-bit bytes, 16-bit words or 32-bit double words. The TI486SLC/E bus architecture allows for bus transfers of these operands without restrictions on physical address alignment. Any byte boundary may require more than one bus cycle to transfer the operand. This feature is transparent to the programmer. 3-17
Functional Timing The TI486SLC/E data bus (015-00) is a 16-bit-wide bidirectional bus. The TI486SLC/E drives the data bus during write bus cycles, and the external system hardware drives the data bus during read bus cycles. The address bus provides a 24-bit value using 23 signals for the 23 upper-order address bits (A23-A 1), defining which 16-bit word is being accessed, and two byte enable signals (SHE and SLE) to directly indicate which of the two bytes within the word are active. Every bus cycle begins with the assertion of the address strobe (ADS). ADS indicates that the TI486SLC/E has issued a new address and new bus cycle definition signals. A bus cycle is defined by four signals: MilO, WiR, o/c and LOCK. MilO defines if a memory or 1/0 operation is occurring, wif5.. defines the cycle to be read or write, and o/c indicates whether a data or control cycle is in effect. LOCK indicates that the current cycle is a locked bus cycle. Every bus cycle completes when the system hardware returns READY asserted. The TI486SLC/E performs the following bus cycle types: • Memory read • Locked memory read • Memory write • Locked memory write • 1/0 read (or coprocessor read) • 1/0 write (or coprocessor write) • Interrupt acknowledge (always locked) • Halt/shutdown When the TI486SLC/E microprocessor has no pending bus requests, the bus enters the idle state. There is no encoding of the idle state on the bus cycle definition signals; however, the idle state can be identified by the absence of further assertions of ADS following a completed bus cycle. 3-18 TI486SLCIE Bus Interface
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
Page 62 and 63: Register Set Table 2-9. TI486DLCIE
Page 64 and 65: Register Set Table 2-12. ARR 1-ARR4
Page 66 and 67: Register Set 2.3.2.6 Test Registers
Page 68 and 69: Register Set Table 2-14. TR6 and TR
Page 70 and 71: Address Spaces 2.4 Address Spaces T
Page 72 and 73: Address Spaces 2.4.2 Memory Address
Page 74 and 75: Address Spaces Figure 2-21. Real Mo
Page 76 and 77: Address Spaces Figure 2-24. Paging
Page 78 and 79: Interrupts and Exceptions 2.5 Inter
Page 80 and 81: Interrupts and Exceptions 2.5.3 Int
Page 82 and 83: Interrupts and Exceptions Table 2-2
Page 84 and 85: System Management Mode 2.6 System M
Page 86 and 87: System Management Mode Figure 2-29.
Page 88 and 89: System Management Mode The new SMM
Page 90 and 91: System Management Mode During SMM o
Page 92 and 93: Protection The Current Privilege Le
Page 94 and 95: Virtual 8086 Mode 2.9 Virtual 8086
Page 96 and 97: TI486SLC/E Bus Interface 3-1
Page 98 and 99: Chapter 3 TI486SLC/E Bus Interface
Page 100 and 101: Overview Table 3-1. TI486SLCIE Sign
Page 102 and 103: Overview Table 3-2. Terminal Functi
Page 108 and 109: Overview 3.1.1 Bus Cycle Definition
Page 110 and 111: Overview Table 3-5 shows the state
Page 114 and 115: Functional Timing 3.2.2.1 Bus Cycle
Page 116 and 117: Functional Timing Non-Pipelined Wai
Page 118 and 119: Functional Timing Because of the de
Page 120 and 121: Functional Timing Pipelined Wait St
Page 122 and 123: Functional Timing Initiating and Ma
Page 124 and 125: Functional Timing Figure 3-12. Comp
Page 126 and 127: Functional Timing Figure 3-13. Inte
Page 128 and 129: Functional Timing Shutdown Indicati
Page 130 and 131: Functional Timing Figure 3-17. Pipe
Page 132 and 133: Functional Timing As shown in Figur
Page 134 and 135: Functional Timing Figure 3-19. Requ
Page 136 and 137: Functional Timing Figure 3-21. Requ
Page 138 and 139: Functional Timing Figure 3-22. 8MI
Page 140 and 141: Functional Timing HALT Initiated Su
Page 142 and 143: Functional Timing 3.2.12 Float Figu
Page 144 and 145: TI486DLC/E Bus Interface 4-1
Page 146 and 147: Chapter 4 TI486DLC/E Bus Interface
Page 148 and 149: Overview Table 4-1. TI486DLCIE SIgn
Page 156 and 157: Overview Table 4-6. Signal States D
Page 158 and 159: Overview 4.1.2 Power Management 4.1
Page 160 and 161: Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing Figure 4-23. Requ
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
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DC Electrical Characteristics Table
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AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
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Pin Assignments Table 6-1. TI486SLC
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Pin Assignments Figure 6-3. TI486DL
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Package Dimensions 6.2 Package Dime
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Thermal Characteristics 6.3 Thermal
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Instruction Set 7-1
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Chapter 7 Instruction Set This sect
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Instruction Fields 7.2 Instruction
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Instruction Fields 7.2.5 reg Field
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Instruction Fields Table 7-7. mod r
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Instruction Fields 7.2.11 sreg3 Fie
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Clock Count Summary 7.4 Clock Count
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--- --;.J -L 01 Table 7-17. Instruc
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I . ~ -.....J Table 7-17. Instructi
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Table 7-17. Instructions, Opcodes,
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-....J N (J.) Table 7-17. Instructi
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I I i I i Table 7-17. Instructions,
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...... ...... '" Table 7-17. Instru
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-....J N co Table 7-17. Instruction
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"-.I ~ Table 7-17. Instructions, Op
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U Appendix A TI486 SMM Pro rammer's
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SMM Implementation A.2 SMM Implemen
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Figure A-1. SMM Memory Space Header
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SMM Implementation 6) NMI is the on
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Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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TI486 Microprocessor - Al Kossow's Bitsavers

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