TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
4.2.12 Power Management
SUSP Initiated Suspend Mode
The TI486DLC/E enters suspend mode when the SUSP input is asserted and
execution of the current instruction, any pending decoded instructions and
associated bus cycles are completed. The TI486DLC/E also waits for the
coprocessor to indicate a not busy status (BUSY =1) prior to entering suspend
mode. The SUSPA output is then asserted. The TI486DLC/E responds to
SUSP and asserts SUSPA only if the SUSP bit is set in the CCRD configuration
register.
Figure 4-27 illustrates the, TI486DLC/E functional timing for SUSP initiated
suspend mode. SUSP is sampled on the phase 2 CLK2 rising edge and must
meet specified setup and hold times to be recognized at a particular CLK2
edge. The time from assertion of SUSP to activation of SUSPA varies
depending on which instructions were decoded priorto assertion of SUSP. The
minimum time from SUSP sampled active to SUSPA asserted is 2 CLK2s. As
a maximum, the TI486DLC/E may execute up to two instructions and
associated bus cycles prior to asserting SUSPA. The time required for the
TI486DLC/E to deactivate SUSPA once SUSP has been sampled inactive is
4 CLK2s.
If the TI486DLC/E is in a hold acknowledge state and SUSP is asserted, the
processor mayor may not enter suspend mode depending on the state of the
TI486DLC/E internal execution pipeline. If the TI486DLC/E is in a SUSP
initiated suspend state and the CLK2 input is not stopped, the processor
recognizes and acknowledges the HOLD input and stores the occurrence of
FLUSH, NMI and INTR (if enabled) for execution once suspend mode is
exited.
Figure 4-27. SUSP Initiated Suspend Mode
1 I 2 I 1 I 2 I 1 I 2
1 I 2 1 I 2 1 I 2
CLK2
e_--- 4 CLK2s -----1.~1
I
I
I
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