TI486 Microprocessor - Al Kossow's Bitsavers

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SMM Implementation A.2 SMM Implementation The following sections provide an overview of TI486 SMM coding and information helpful in developing SMM code. A.2.1 Hardware Background A.2.1.1 SMM Pins A.2.1.2 SMI Pin Timing A.2.1.3 Address Strobes The SMI and SMADS pins are used to implement SMM. The bidirectional SMI pin is used by the chip set to signal the CPU that an SMI has occurred. While the CPU is in the process of servicing an SMM interrupt, the same pin is used to send a signal to the chip set to indicate that the SMM processing is occurring. The SMADS address strobe is generated instead of the ADS address strobe while executing or accessing data in SMM address space. In order to enter TI486 SMM mode, the SMI pin must be asserted for at least 4 CLK2 periods. Once the CPU recognizes the active SMI input, the CPU drives the SMI input low for the duration of the SMI routine. The SMI routine is terminated with an SMI specific resume RSM instruction. When the RSM instruction is executed, the CPU drives the SMI pin high for 2 CLK2 periods. The SMI pin bidirectional design: 1) Prohibits more than one SMI interrupt from becoming active. 2) Provides feedback to the chip-set/core logic that an SMI is in process. 3) Provides compatibility with other SMM hardware interfaces. The TI486 CPU has two address strobes, ADS and SMADS. ADS is the address strobe used during normal operations. The SMADS address strobe replaces ADS during SMM operations when data is written, read, or fetched in the SMM defined region. Using a separate address strobe increases chip set compatibility and control. During an SMM interrupt routine, control can be transferred to main memory via a JMP, CALL, Jcc instruction or execution of a software interrupt (INT). Execution in main memory will cause ADS to be generated for code and data outside of the defined SMM address region. (It is assumed, but not required, that the chip set ultimately translates SMADS and a particular address to some other address.) To access code in main memory that overlaps the SMM address space, the MMAC bit (CCR1, bit 3) must be set. This allows ADS strobes to be generated for MOV instructions that overlap main memory while in SMM mode. It is not possible to execute code in main memory that overlaps SMM space while in the SMM mode. SMADS can also be generated for memory reads/writes and code fetches within the defined SMM region when the SMAC bit (CCR1 , bit 2) is set while in normal mode. The generation of SMADS would permit a program in normal A-3
SMM Implementation A.2.1.4 Chip-Set READY space to jump into SMM code space. Care should be taken to be in real mode before the jump occurs into SMM space. A routine should be followed to initialize used registers to their real-mode state. The RSM instruction should not be used after jumping into SMM space unless return information is first written into the SMM context area before the RSM instruction is executed. The TI486 CPU has one READY input. Chip sets that implement the dual READY lines can OR the two ready lines together for the single READY. The AMD implementation of SMM provides for two READY lines from the chip set, one for SMM space (SREADY) and one for the normal READY. A.2.2 SMM Software Considerations A.2.2.1 SMM Handler Entry State At the start of the SMM routine, before control is transferred to code executing at SMM base, some of the CPU state is saved at the end of SMM memory. This is one area where the TI486 CPU SMM state is unique. The CPU saves the minimum CPU state information necessary for an interrupt handler to execute and return to the interrupted context. The information is saved at the top of the defined SMM region (starting at SMM base + size - 30h). Of the typically used program registers only the CS, EFLAGS, CRO, and DR7 are saved upon entry. This requires that data accesses use a CS segment override to save other registers and access data. To use any other register the SMM programmer must first save the contents using the SVDC instruction for segment registers or MOV operations for general purpose registers (See SMM Instructions, Section A.12). It is possible to save all the CPU registers as needed. Unique to the TI486 CPU is the saving of the previous IP, before the SMI, and the next IP to be executed after exiting the SMI handler. Upon execution of an RSM instruction, control is returned to the "next IP". The value of the "next IP" may need to be modified for restarting OUTSxllNSx instructions; this modification is a simple move (MOV) of the "previous IP" value to the "next IP" location. Execution is then returned to the I/O instruction, rather than the instruction after the next I/O instruction. (The restarting of I/O instructions may also require modifications to the ESI, ECX, and EDI depending on the instruction. See Section A.S for an example.) Figure A-1 and Table A-1 describe the SMM memory space header. The P and I bits indicate whether a INSxlOUTSx and REP prefix were being executed. IN/OUT instructions will be restarted by changing "NEXT IP" and leaving the SMI handler. The only area in the SMM header that the programmer should consider altering is the "NEXT IP". Altering any other header values can have unpredictable results. The EFLAGS, CRO, and DR7 registers are set to the reset values upon entry to the SMI handler. This has implications for setting break points using the debug registers. Break points can not be set prior to the SMI using debug A-4 TI486 SMM Programmer's Guide
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
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DC Electrical Characteristics Table
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AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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AC Characteristics Figure 5-10. TI4
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Page 220 and 221: Mechanical Specifications 6-1
Page 222 and 223: Chapter 6 Mechanical Specifications
Page 224 and 225: Pin Assignments Table 6-1. TI486SLC
Page 226 and 227: Pin Assignments Figure 6-3. TI486DL
Page 228 and 229: Package Dimensions 6.2 Package Dime
Page 230 and 231: Thermal Characteristics 6.3 Thermal
Page 232 and 233: Instruction Set 7-1
Page 234 and 235: Chapter 7 Instruction Set This sect
Page 236 and 237: Instruction Fields 7.2 Instruction
Page 238 and 239: Instruction Fields 7.2.5 reg Field
Page 240 and 241: Instruction Fields Table 7-7. mod r
Page 242 and 243: Instruction Fields 7.2.11 sreg3 Fie
Page 244 and 245: Clock Count Summary 7.4 Clock Count
Page 246 and 247: --- --;.J -L 01 Table 7-17. Instruc
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Page 250 and 251: Table 7-17. Instructions, Opcodes,
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Page 260 and 261: -....J N co Table 7-17. Instruction
Page 262 and 263: "-.I ~ Table 7-17. Instructions, Op
Page 266 and 267: U Appendix A TI486 SMM Pro rammer's
Page 270 and 271: Figure A-1. SMM Memory Space Header
Page 272 and 273: SMM Implementation 6) NMI is the on
Page 274 and 275: Instruction Summary A.4 Instruction
Page 276 and 277: Instruction Summary A.4.3 Resume No
Page 278 and 279: Instruction Summary A.4.6 Save LDTR
Page 280 and 281: 8MI Handler Example A.5 SMI Handler
Page 282 and 283: 8MI Handler Example execute_halt: C
Page 284 and 285: 8MI Handler Example COMMENT A The T
Page 286 and 287: 8MI Handler Example arrl arr2 arr3
Page 288 and 289: .MODEL SMALL . STACK .386P INCLUDE
Page 290 and 291: Testing/Debugging SMM Code sgdt COM
Page 292 and 293: Testing/Debugging SMM Code i*******
Page 294 and 295: TI486 Power Management Features A.7
Page 296 and 297: Detection of Tl486 CPU A.9 Detectio
Page 298 and 299: Detection of SMM Capable Version A.
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Page 302 and 303: A.11 SMM Feature Comparison SMM Fea
Page 304 and 305: SMM Instruction Macros COMMENT A Co
Page 306 and 307: SMM Instruction Macros SMM Instruct
Page 308 and 309: A.14 Format of Data Used by SVDC/RS
Page 310 and 311: Altering SMM Code Limits A.1S Alter
Page 312 and 313: SMM Errata A.16 SMM Errata The foll
Page 314 and 315: Appendix B TI486 Cache Flush B.1 Ge
Page 316 and 317: Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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