TI486 Microprocessor - Al Kossow's Bitsavers

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U Appendix A TI486 SMM Pro rammer's Guide This programmers guide provides detailed information, including example code listings, macros, and instructions, pertinent to the TI486 system management modes (SMM). Topic Page A.1 ; SUM Overview A;"2 ..;. .;..... ~'.;,; :'··~~::A~3. 'A2 ~!~i~~~~f'} A~3 ~na~'Jng:$f4M .. A.4·. In~trUjti()n'~uT~a~ "; ~ .." "; ,....:; ". , - .. : "::. ::" :f::.~:·\t:·:: \ ~~ "::.:: Y;·':;;:· ~: ... {." ·:~···A~~:; , .. - "' A;"15 A~5~~fHarl~.I~;r.~~~TPI~ ..; ...;•.. .•;.... ;.;......;.;..•... A.S,· .;·"(esth'9I:[)el:)",ggi"g.. $MM··.Co~e> ;···A.. 22 A.i· .tI4~f5.j;J~~~rl\ll~t)a~.e~~~tF~f~~.; .""...;......".............'. .... ..... ........ ;;............. ....... ...:~~9 " , ".": "... :::: ';'. ;.. ". :. ".. ":.~:' '. ".':' ". ".... ". ':' .". -......" :'. . . ' .... ' ::: ....:.. :'. . '. .:'. "'::". :. '.', ". .' .." ," ;, ... ".".". . ~ ..;" •••:'.' :::: "." ..:' .." ":.. ' ".'".....:," ":.". ',.: .'":". :. ":..': :. ". :".': ,".' .'.' : ." ":.:..:. ".. "."..:' ".:' ::: ': :. :. -: ': .. ". "'. : .:: ': ': ":.:. '.: :: :. ".:. :.::;. :::.::.: .:...:.- .: .....:: A.S LQat1ingSIVlMl\llemorv··.VVitha"SMqPI'Qg~rofrQm· .. Maifl.MeI1lQ.;y .A.. ~. A.9Detectioll.ofTI486CPU A .• 10.·· ... t1et~bil~n.··~f·.~I\JI~ .•.··¢ap~blev'.:s~6i1 .'.. , ... ..:.. : ."::... : :::.: .".. -. ... -:-:.: ....... ~: .......: '. ' ~;11SJ.tLJI=$!IJ~~Ol1Ipar~~~.·.···.·.·.\i··· ,. ~.111· $MM~~U~IJ)It+S:SMIMAC.INe·· A.13· TJ486DlCIEahdSMM .A.14 •.... ~QrT~tofDat~ •• Qs'~BY .•• ~vDt!R~t1C .. lrI~tr~~tiotis .~.~1.5.·...·.. Alt'ri~.g~ ... L1 ..... ~Qde •.. ~il1lit$ . A~16' SMft/I •. Addendum. A~9 A.;;31··· ~ .: :.:......... :....... ,. ·;Ai.33 .A.i.S7 A .. SQ ·······.···A42 , ... '.' ···A"47 A-1
SMMOveNiew A.1 SMM Overview A.1.1 Introduction This programmer's guide has been written to aid programmers in the creation of software using the TI486 system management mode (SMM). SMM is currently implemented in both the TI486SLC/E and the TI486DLC/E, and the 3-volt versions of each (TI486xLC/E-V) microprocessor. For an introduction to SMM and additional information, refer to the Tl48632-8it Microprocessor Reference Guide. Section A.13 describes the differences between the TI486SLC/E and the TI486DLC/E with SMM. Section A.16 contains important information concerning SMM programming. A.1.2 SMM Implementation SMM operation in the TI486 microprocessors is similar to related operations performed by the AMD and Intel microprocessors. Each of these three microprocessors switches into real mode upon entry into the SMM interrupt handler. Each manufacturer's CPU has unique SMM code locations. The TI CPU has a programmable location and size for the SMM memory region. Each of the manufacturer's processors saves the programmer-visible register contents upon entry and also saves the non-programmer visible register contents. The TI486 CPU automatically saves the minimal register information, reducing the entry and exit clock count to 140. This compares with Intel's clock overhead for entry and exit of 804 clocks and AMD's minimum of 694 clocks. (See Section A.11 for a comparison of SMM overhead.) The TI486 SMM implementation provides unique instructions that save additional segment registers as required by the programmer, in addition to the x86 MOV instruction that saves the general purpose registers. Although all three manufacturer's CPUs provide liD trapping, the TI486 SMM simplifies identification of liD type and instruction restarting. The TI486 SMM process is unique in its ability to permit software relocation and sizing of the SMM address region. This flexibility facilitates run time changes to SMM support. This software flexibility allows an operating system or debugger to change, modify, or disable the SMM code. A-2 Tl486 SMM Programmer's Guide
Page 1 and 2:
.TEXAS INSTRUMENTS TI486 Microproce
Page 4 and 5:
TI486 Microprocessor Reference Guid
Page 6 and 7:
Preface Read This First About This
Page 8 and 9:
About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
Page 22 and 23:
Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
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DC Electrical Characteristics Table
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AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
Page 216 and 217: AC Characteristics Figure 5-10. TI4
Page 218 and 219: AC Characteristics Figure 5-12. TI4
Page 220 and 221: Mechanical Specifications 6-1
Page 222 and 223: Chapter 6 Mechanical Specifications
Page 224 and 225: Pin Assignments Table 6-1. TI486SLC
Page 226 and 227: Pin Assignments Figure 6-3. TI486DL
Page 228 and 229: Package Dimensions 6.2 Package Dime
Page 230 and 231: Thermal Characteristics 6.3 Thermal
Page 232 and 233: Instruction Set 7-1
Page 234 and 235: Chapter 7 Instruction Set This sect
Page 236 and 237: Instruction Fields 7.2 Instruction
Page 238 and 239: Instruction Fields 7.2.5 reg Field
Page 240 and 241: Instruction Fields Table 7-7. mod r
Page 242 and 243: Instruction Fields 7.2.11 sreg3 Fie
Page 244 and 245: Clock Count Summary 7.4 Clock Count
Page 246 and 247: --- --;.J -L 01 Table 7-17. Instruc
Page 248 and 249: I . ~ -.....J Table 7-17. Instructi
Page 250 and 251: Table 7-17. Instructions, Opcodes,
Page 254 and 255: -....J N (J.) Table 7-17. Instructi
Page 256 and 257: I I i I i Table 7-17. Instructions,
Page 258 and 259: ...... ...... '" Table 7-17. Instru
Page 260 and 261: -....J N co Table 7-17. Instruction
Page 262 and 263: "-.I ~ Table 7-17. Instructions, Op
Page 268 and 269: SMM Implementation A.2 SMM Implemen
Page 270 and 271: Figure A-1. SMM Memory Space Header
Page 272 and 273: SMM Implementation 6) NMI is the on
Page 274 and 275: Instruction Summary A.4 Instruction
Page 276 and 277: Instruction Summary A.4.3 Resume No
Page 278 and 279: Instruction Summary A.4.6 Save LDTR
Page 280 and 281: 8MI Handler Example A.5 SMI Handler
Page 282 and 283: 8MI Handler Example execute_halt: C
Page 284 and 285: 8MI Handler Example COMMENT A The T
Page 286 and 287: 8MI Handler Example arrl arr2 arr3
Page 288 and 289: .MODEL SMALL . STACK .386P INCLUDE
Page 290 and 291: Testing/Debugging SMM Code sgdt COM
Page 292 and 293: Testing/Debugging SMM Code i*******
Page 294 and 295: TI486 Power Management Features A.7
Page 296 and 297: Detection of Tl486 CPU A.9 Detectio
Page 298 and 299: Detection of SMM Capable Version A.
Page 300 and 301: i**********************************
Page 302 and 303: A.11 SMM Feature Comparison SMM Fea
Page 304 and 305: SMM Instruction Macros COMMENT A Co
Page 306 and 307: SMM Instruction Macros SMM Instruct
Page 308 and 309: A.14 Format of Data Used by SVDC/RS
Page 310 and 311: Altering SMM Code Limits A.1S Alter
Page 312 and 313: SMM Errata A.16 SMM Errata The foll
Page 314 and 315: Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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