TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
Non-Pipelined Read and Write Cycles
Any bus cycle may be performed with non-pipelined address timing.
Figure 3-5 shows a mixture of read and write cycles with non-pipelined
address timing. When a read cycle is performed, the TI486SLC/E
microprocessor floats its data bus and the externally addressed device then
drives the data. The TI486SLC/E microprocessor requires that all data bus
pins be driven to a valid logic state (high or low) at the end of each read cycle,
when READY is asserted. When a read cycle is acknowledged by READY
asserted in the T2 bus state, the TI486SLC/E CPU latches the information
present at its data pins and terminates the cycle.
When a write cycle is performed, the data bus is driven by the TI486SLC/E
CPU beginning in phase two of T1. When a write cycle is acknowledged, the
TI486SLC/E write data remains valid throughout phase one of the next bus
state to provide write data hold time.
Figure 3-5. Various Non-Pipelined Bus Cycles (No Wait States)
I I Cycle 1 I Cycle 2 I Cycle 3 I
I Idle I Non-Pipelined I Non-Pipelined I Non-Pipelined I Idle
I I (Write) I (Read) I (Write) I
I I I I I
I Ti I T1 T2 I T1 I T1 I Ti
Cycle 4
Non-Pipelined
(Read)
T1
I
I Idle
I
I
I Ti
CLK2
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