TI486 Microprocessor - Al Kossow's Bitsavers

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TI486 Power Management Features A.7 TI486 Power Management Features The TI486 CPU provides several methods and levels of power management. The fully static design, suspend mode, system management mode (SMM), and 3.3-volt operation can be used to achieve optimum CPU and system power management. The following table summarizes the various power management options for the T1486: Option Reduced Clock Frequency Lower Supply Voltage (V CC) Suspend Mode Remove Clock Power Savings ICC = (12 x fCLK2 (MHz)) + 150 rnA @ 5 V ICC = (130 x VCC) - 256 rnA @ 25 MHz 20/0 of typical ICC 250/0 of typical ICC Suspend Mode and Remove Clock 400~A Remove Power O~A A.7.1 Reducing the Clock Frequency The TI486 CPU is a fully static design meaning that the input clock frequency can be reduced or stopped without a loss of internal CPU data or state. The system designer can make decisions to reduce the clock by utilizing the SMM capabilities to support Advanced Power Management (APM) software API in concert with chip set capabilities. When the clock is removed then restarted, CPU execution will begin with the instruction where the clock was removed. A.7.2 Suspend Mode The TI486 CPU supports suspend mode operation that can be entered either through software or hardware initiation. Software initiates suspend mode through execution of a HALT instruction. After HALT is executed, the CPU enters suspend mode and asserts suspend acknowledge (SUSPA), if enabled. Hardware initiates suspend mode by using the SUSP and SUSPA pins of the T1486. When SUSP is asserted the CPU completes any pending instructions and bus cycles and then enters suspend mode. Once in suspend mode, the SUSPA pin is asserted by the CPU. A-29
Loading SMM Memory A.8 Loading SMM Memory With an SMM Program from Main Memory SMI 1 SMAC 1 MMAC 1 SM4 1 To load SMM memory with an 8MI interrupt handler it is important that the SMI interrupt does not occur before the handler is ready to accept it. This can be done by not having SMAC = 0 and SM I = 1 (in the CCR 1 register) before the 8MI handler is installed. It is necessary to set SM4 = 1 and ARR4 with appropriate values before using the SMM memory. To load SMM memory with a program it is first necessary to enable SMM with the exception of the SMI pin by setting SMAC. (See Section A.3.) The SMM region is then mapped over main memory at the same location. This is done by the generation of SMADS for memory access for the SMI. A REP MOV instruction can then be used to transfer the program to the location. Then, turn off SMAC to activate potential 8Mls. shl 1 shl 2 shl 3 shl 7 mov out in mov mov out mov or out mov mov mov mov mov mov rep mov out in mov mov out mov and out al, Oclh 22h, al al, 23h ah,al al, Oclh 22h, al al, ah al, SMI or SMACi 23h, al ax, SMI_SEGMENT es, ax edi, 0 index to CCrl select CCRl register read current CCRl value index to CCRl select CCRl register write new value to CCRl istart of the SMM area esi, offset SMI_ROUTINE ds,seg SMI_ROUTINE ecx, (SMI_ROUTINE_LENGTH+3)/4 movs dword ptr es: [edi],dword ptr ds: [esi] al,Oclh index to CCRl 22h, al select CCRl register al, 23h ah,al al, Oclh 22h, al al, ah al,NOT SMAC 23h, al read current CCRl value index to CCRl select CCRl register idisable SMAC, enable SMI# i write new value to CCRl A-30 TI486 SMM Programmer's Guide
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
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DC Electrical Characteristics Table
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AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
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Pin Assignments Table 6-1. TI486SLC
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Pin Assignments Figure 6-3. TI486DL
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Package Dimensions 6.2 Package Dime
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Thermal Characteristics 6.3 Thermal
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Instruction Set 7-1
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Chapter 7 Instruction Set This sect
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Instruction Fields 7.2 Instruction
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Instruction Fields 7.2.5 reg Field
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Instruction Fields Table 7-7. mod r
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Instruction Fields 7.2.11 sreg3 Fie
Page 244 and 245: Clock Count Summary 7.4 Clock Count
Page 246 and 247: --- --;.J -L 01 Table 7-17. Instruc
Page 248 and 249: I . ~ -.....J Table 7-17. Instructi
Page 250 and 251: Table 7-17. Instructions, Opcodes,
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Page 258 and 259: ...... ...... '" Table 7-17. Instru
Page 260 and 261: -....J N co Table 7-17. Instruction
Page 262 and 263: "-.I ~ Table 7-17. Instructions, Op
Page 266 and 267: U Appendix A TI486 SMM Pro rammer's
Page 268 and 269: SMM Implementation A.2 SMM Implemen
Page 270 and 271: Figure A-1. SMM Memory Space Header
Page 272 and 273: SMM Implementation 6) NMI is the on
Page 274 and 275: Instruction Summary A.4 Instruction
Page 276 and 277: Instruction Summary A.4.3 Resume No
Page 278 and 279: Instruction Summary A.4.6 Save LDTR
Page 280 and 281: 8MI Handler Example A.5 SMI Handler
Page 282 and 283: 8MI Handler Example execute_halt: C
Page 284 and 285: 8MI Handler Example COMMENT A The T
Page 286 and 287: 8MI Handler Example arrl arr2 arr3
Page 288 and 289: .MODEL SMALL . STACK .386P INCLUDE
Page 290 and 291: Testing/Debugging SMM Code sgdt COM
Page 292 and 293: Testing/Debugging SMM Code i*******
Page 296 and 297: Detection of Tl486 CPU A.9 Detectio
Page 298 and 299: Detection of SMM Capable Version A.
Page 300 and 301: i**********************************
Page 302 and 303: A.11 SMM Feature Comparison SMM Fea
Page 304 and 305: SMM Instruction Macros COMMENT A Co
Page 306 and 307: SMM Instruction Macros SMM Instruct
Page 308 and 309: A.14 Format of Data Used by SVDC/RS
Page 310 and 311: Altering SMM Code Limits A.1S Alter
Page 312 and 313: SMM Errata A.16 SMM Errata The foll
Page 314 and 315: Appendix B TI486 Cache Flush B.1 Ge
Page 316 and 317: Appendix C TI486 BIOS Modification
Page 318 and 319: Introduction Some example assembler
Page 320 and 321: Appendix D Ordering Information 0.1
Page 322: ~TEXAS INSTRUMENTS Printed in U.S.A
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