TI486 Microprocessor - Al Kossow's Bitsavers

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Preface Read This First About This Manual This manual describes both the TI486SLC/E and TI486DLC/E product family. Each chapter except for chapters 3 and 4 cover both the TI486SLC/E and TI486DLC/E. Chapter 3 explicitly covers the TI486SLC/E and chapter 4 explicitly covers the TI486DLC/E. This document contains the following chapters: Chapter 1 Product Overview Chapter 1 introduces the features and itemizes the differences between the TI486SLC/E and TI486DLC/E, both of which are offered in 3-volt versions (TI486xLC/E-V) for battery-powered applications. A functional block diagram, logic symbol, and 1/0 signal pins are provided for each of the two microprocessors. Additional material describes selected system architectures such as the execution pipeline, the on-chip cache memory, and the power management techniques. The System Management Mode (SMM) permits the TI486 microprocessors to respond to and service interrupts having a higher priority than standard 486 processors. Chapter 2 Programming Interface Chapter 2 describes the internal operations of the T1486, for both the TI486SLC/E and TI486DLC/E, mainly from an application programmer's point of view. Included in this chapter are descriptions of processor initialization, the register set, memory addressing, various types of interrupts, and the shutdown and halt process. Also included is an overview of real, virtual 8086, and protected operating modes. Chapter 3 TI486SLC/E Bus Interface Chapter 3 provides an overview of the TI486SLC/E processor signals, functional description of all pins, functional timing and bus operations (including non-pipelined and pipelined addressing), interfaces, and power management. v
About This Manual Chapter 4 TI486DLC/E Bus Interface Chapter 4 provides an overview of the TI486DLC/E processor signals, functional description of all pins, functional timing and bus operations (including non-pipelined and pipelined addressing), interfaces, and power management. Chapter 5 Electrical Specifications Chapter 5 provides electrical specifications for both the TI486SLC/E and TI486DLC/E, including specifications for the 3-volt versions. The specifications include electrical connection requirements for all package types and pins, maximum ratings, recommended operating conditions, dc electrical, and ac characteristics. Chapter 6 Mechanical Specifications Chapter 6 provides mechanical specifications for both the TI486SLC/E and TI486DLC/E that include pin assignments, package physical dimensions, and package thermal characteristics. Chapter 7 Instruction Set Chapter 7 summarizes the TI486 instruction set and provides detailed information of the instruction encodings. The instruction set is the same for all TI486 processors. Instructions are listed in an instruction set summary table, that also provides information on the flags affected and the instruction clock counts for each instruction. Appendix A TI486 SMM Programmer's Guide Appendix A provides detailed information, including examples pertinent to programming the TI486 system management mode (SMM). Included are SMI examples, testing/debugging SMM code, power management features, loading SMM programs, detection of CPU type and presence of SMM-capable devices, creating macros, and altering SMM code limits. Appendix B TI486 Cache Flush Appendix B provides general cache invalidation techniques and discusses invalidation in systems with and without secondary cache. Appendix C TI486 BIOS Modification Guide Appendix C discusses some BIOS changes that may need to be considered by the PC designer. The areas considered are power-on and hard reset, protected-mode to real-mode switching, and soft reset. Examples of assembler code for turning the cache on and off are provided. vi Read This First
Page 1 and 2: .TEXAS INSTRUMENTS TI486 Microproce
Page 4 and 5: TI486 Microprocessor Reference Guid
Page 8 and 9: About This Manual Appendix D Orderi
Page 10 and 11: Contents 1 Product Overview .......
Page 12 and 13: Contents 5.5 AC Characteristics . .
Page 14 and 15: 1-1 TI486SLC/E Functional Block Dia
Page 16 and 17: Figures 4-27 SUSP Initiated Suspend
Page 18 and 19: Tables 5-3 Absolute Maximum Ratings
Page 20 and 21: Product Overview 1-1
Page 22 and 23: Chapter 1 Product Overview Features
Page 24 and 25: 1.2 Differences Between the TI486SL
Page 26 and 27: Tl486SLCIE Overview Figure 1-2. TI4
Page 28 and 29: Tl486DLCIE Overview 1.4 TI486DLC/E
Page 30 and 31: TI486DLCIE Overview The TI486DLC/E
Page 32 and 33: Power Management / System Managemen
Page 34 and 35: Programming Interface 2-1
Page 36 and 37: Chapter 2 In this chapter, the inte
Page 38 and 39: Processor Initialization Table 2-1.
Page 40 and 41: Instruction Set Overview 2.2 Instru
Page 42 and 43: Register Set 2.3 Register Set There
Page 44 and 45: Register Set Pointer and Index Regi
Page 46 and 47: Register Set 2.3.1.2 Segment Regist
Page 48 and 49: Register Set 2.3.1.3 Instruction Po
Page 50 and 51: Register Set 2.3.2 System Register
Page 52 and 53: Register Set 2.3.2.1 Control Regist
Page 54 and 55: Register Set 2.3.2.2 Descriptor Tab
Page 56 and 57:
Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Page 106 and 107:
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
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DC Electrical Characteristics Table
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AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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Page 218 and 219:
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Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
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Pin Assignments Table 6-1. TI486SLC
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Pin Assignments Figure 6-3. TI486DL
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Package Dimensions 6.2 Package Dime
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Thermal Characteristics 6.3 Thermal
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Instruction Set 7-1
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Chapter 7 Instruction Set This sect
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Instruction Fields 7.2 Instruction
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Instruction Fields 7.2.5 reg Field
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Instruction Fields Table 7-7. mod r
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Instruction Fields 7.2.11 sreg3 Fie
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Clock Count Summary 7.4 Clock Count
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--- --;.J -L 01 Table 7-17. Instruc
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I . ~ -.....J Table 7-17. Instructi
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Table 7-17. Instructions, Opcodes,
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-....J N (J.) Table 7-17. Instructi
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I I i I i Table 7-17. Instructions,
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...... ...... '" Table 7-17. Instru
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-....J N co Table 7-17. Instruction
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"-.I ~ Table 7-17. Instructions, Op
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U Appendix A TI486 SMM Pro rammer's
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SMM Implementation A.2 SMM Implemen
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Figure A-1. SMM Memory Space Header
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SMM Implementation 6) NMI is the on
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Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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i**********************************
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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