TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
Figure 4-8. Fastest Pipelined Read Cycles
Cycle 1 I Pipelined I
(Read)
I T1P T2P I
I 2: 1 I 2 I
CLK2
Cycle 2 I
Pipelined I
(Read)
T1P I T2P I
2 I 1 I 2 I
Cycle 3
Pipelined I
(Read)
T1P I T2P I
2 I 1 I 2 I
A31-A2, BE3-BEO,
MIlO, Die, wiR
--~----~~~----~----~~~----~----~~~----~---
NA
031-00
(Input During Read)
Valid 1 P.
Valid
I I I
2 p.
Valid
3 ~
I I I
I I I I I I I
~--~--~--~--~--~--~
I : I : I : I
Note:
Fastest pipelined bus cycles consist of T1 P and T2P.
Within the pipelined bus cycle, NA is sampled at the beginning of phase 2 of
the T1 P state. If the TI486DLC/E has an internally pending bus request and
NA is asserted, the T1 P state is followed by a T2P state and the address and
bus cycle definition for the next pending bus request is made available. If no
pending bus request exists, the T1 P state is followed by a T21 state regardless
of the state of NA and no new address or bus cycle information is driven.
The pipelined bus cycle is terminated in either the T2P or T21 states with the
assertion of the READY input and valid data is either input or output depending
on the bus cycle type. READY is ignored at the end of the T1 P state.
Pipelined Read and Write Cycles
Any bus cycle may be performed with pipelined address timing. When a read
cycle is performed, the TI486DLC/E microprocessor floats its data bus and the
externally addressed device then drives the data. When a read cycle is
acknowledged by READY asserted in either the T2P or T21 bus state, the
TI486DLC/E CPU latches the information present at its data pins and
terminates the cycle.
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