TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
Figure 4-25. 8MI Timing
CLK2
(Input)
:;
'+---+----t--~~ 't!--.......... "*'I,
Indicates that the TI486DLC/E drives the 8MI pin.
c d e
1
1
4.2.11.2 I/O Trapping
Figure 4-26. liD Trap Timing
The TI486DLC/E provides lID trapping that can be used to facilitate power
management of lID peripherals. When an lID bus cycle is issued, the lID
address is driven onto the address bus and can be decoded by external logic.
If a trap to the 8MI handler is required, the SMI input should be activated at
least three CLK2 edges prior to returning the READY input for the lID cycle.
The timing for creating an lID trap via the 8MI input is shown in Figure 4-26.
The TI486DLC/E immediately traps to the 8MI interrupt handler following
execution of the lID instruction, and no other instructions are executed
between completion of the lID instruction and entering the 8M I service routine.
The lID trap mechanism is not active during coprocessor accesses.
1
14
1/0 CYCLE
(Read or Write)
T1
I
T2
I
T2
I
T2
I
CLK2
(Input)
Address,
Byte Enables
ADS
(Output)
1 1
------...ft.:\ II
1 1
1 1
1
1 I
1 I
1 I
----~--~----~l\~: __ ----~II
1 I 1
3CLK2S!4 ~
4-50
TI486DLCIE Bus Interface