TI486 Microprocessor - Al Kossow's Bitsavers

SMM Implementation
A.2.1.4 Chip-Set READY
space to jump into SMM code space. Care should be taken to be in real mode
before the jump occurs into SMM space. A routine should be followed to
initialize used registers to their real-mode state. The RSM instruction should
not be used after jumping into SMM space unless return information is first
written into the SMM context area before the RSM instruction is executed.
The TI486 CPU has one READY input. Chip sets that implement the dual
READY lines can OR the two ready lines together for the single READY. The
AMD implementation of SMM provides for two READY lines from the chip set,
one for SMM space (SREADY) and one for the normal READY.
A.2.2 SMM Software Considerations
A.2.2.1 SMM Handler Entry State
At the start of the SMM routine, before control is transferred to code executing
at SMM base, some of the CPU state is saved at the end of SMM memory. This
is one area where the TI486 CPU SMM state is unique. The CPU saves the
minimum CPU state information necessary for an interrupt handler to execute
and return to the interrupted context. The information is saved at the top of the
defined SMM region (starting at SMM base + size - 30h). Of the typically used
program registers only the CS, EFLAGS, CRO, and DR7 are saved upon entry.
This requires that data accesses use a CS segment override to save other
registers and access data. To use any other register the SMM programmer
must first save the contents using the SVDC instruction for segment registers
or MOV operations for general purpose registers (See SMM Instructions,
Section A.12). It is possible to save all the CPU registers as needed.
Unique to the TI486 CPU is the saving of the previous IP, before the SMI, and
the next IP to be executed after exiting the SMI handler. Upon execution of an
RSM instruction, control is returned to the "next IP". The value of the "next IP"
may need to be modified for restarting OUTSxllNSx instructions; this
modification is a simple move (MOV) of the "previous IP" value to the "next IP"
location. Execution is then returned to the I/O instruction, rather than the
instruction after the next I/O instruction. (The restarting of I/O instructions may
also require modifications to the ESI, ECX, and EDI depending on the
instruction. See Section A.S for an example.)
Figure A-1 and Table A-1 describe the SMM memory space header. The P
and I bits indicate whether a INSxlOUTSx and REP prefix were being
executed. IN/OUT instructions will be restarted by changing "NEXT IP" and
leaving the SMI handler.
The only area in the SMM header that the programmer should consider
altering is the "NEXT IP". Altering any other header values can have
unpredictable results.
The EFLAGS, CRO, and DR7 registers are set to the reset values upon entry
to the SMI handler. This has implications for setting break points using the
debug registers. Break points can not be set prior to the SMI using debug
A-4
TI486 SMM Programmer's Guide