TI486 Microprocessor - Al Kossow's Bitsavers

Address Spaces
generated by adding the segment base address in the hidden portion of the
segment register to the offset address. If paging is not enabled, this linear
address is used as the physical memory address. Figure 2-23 illustrates the
operation of the selector mechanism.
Figure 2-23. Selector Mechanism
Selector
Load
15
o }
I Index I TI I RPL I Selector
....---,--1 -~--"'
(Accessed
Segment
Register)
...
Segment
Descriptor
TI = 0 TI = 1
r-------;---~8~\ 00-----+-------,
Segment
Descriptor
...
Global Descriptor Table
Local Descriptor Table
-----------------------------------------
Memory
Reference
..
....
Descriptor
Cache
1----.. ~ Base Address
Paging Mechanism
The paging mechanism supports a memory subsystem that simulates a large
address spac~ with a small amount of RAM and disk storage. The paging
mechanism either translates a linear address to its corresponding physical
address or generates an exception if the required page is not currently present
in RAM. When the operating system services the exception, the required page
is loaded into memory and the instruction is then restarted. Pages are always
4 KBytes in size and are aligned to 4-KByte boundaries.
A page is addressed by using two levels of tables as illustrated in Figure 2-24.
The upper 10 bits of the 32-bit linear address are used to locate an entry in the
page directory table. The page directory table acts as.a 32-bit master index to
up to 1 K individual second-level page tables. The selected entry in the page
directory table, referred to as the directory table entry, identifies the starting
address of the second-level page table. The page directory table itself is a
page and is, therefore, aligned to a 4-KByte boundary. The physical address
of the current page directory is stored in the CR3 control register, also referred
to as the Page Directory Base Register (PDSR).
2-42
Programming Interface