TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
Because of the demultiplexed nature of the bus, the address pipelining option
provides a mechanism for the external hardware to have an additional T state
of access time without inserting a wait state. After the reset sequence and
following any idle bus state, the processor always uses non-pipelined address
timing. Pipe lined or non-pipelined address timing is then determined on a
cycle-by-cycle basis using the NA input. When address pipelining is not used,
the address and bus cycle definition remain valid during all wait states. When
wait states are added and it is desirable to maintain non-pipe lined address
timing, it is necessary to negate NA during each T2 state of the bus cycle
except the last one.
4.2.2.2 Bus Cycles Using Pipelined Addressing
The address pipelining option allows the system to request the address and
bus cycle definition of the next internally pending bus cycle before the current
bus cycle is acknowledged with READY asserted. If address pipelining is
used, the external system hardware has an extra T state of access time to
transfer data. The address pipelining option is controlled on a cycle-by-cycle
basis by the state of the NA input.
Pipelined Bus States
Pipelined addressing is always initiated by asserting NA during a
non-pipelined bus cycle. Within the non-pipelined bus cycle, NA is sampled at
the beginning of phase 2 of each T2 state and is only acknowledged by the
TI486DLC/E during wait states. When address pipelining is acknowledged,
the address (BE3-BEO, and A31-A2) and bus cycle definition (WiR, Ole, and
MilO) of the next bus cycle are driven before the end of the non-pipelined
cycle. The address status output (ADS) is asserted simultaneously to indicate
validity of the above signals. Once in effect, address pipelining is maintained
in successive bus cycles by continuing to assert NA during the pipelined bus
cycles.
As in non-pipelined bus cycles, the fastest bus cycles using pipelined address
require only two bus states. Figure 4-8 illustrates the fastest read cycles using
pipelined address timing. The two bus states for pipelined addressing are T1 P
and T2P or T1 P and T21. The T1 P state is entered following completion of the
bus cycle in which the pipe lined address and bus cycle definition information
was made available and is the first bus state of every pipelined bus cycle. In
other words, the T1 P state follows a T2 state if the previous cycle was
non-pipelined, and follows a T2P state if the previous cycle was pipelined.
4-24
T1486DLCIE Bus Interface