TI486 Microprocessor - Al Kossow's Bitsavers

SMM Implementation
6) NMI is the only enabled interrupt at the entry to the SMI handler. It is
advised that system designers provide latches to disable NMI while the
8MI is in progress.
7) The SMI handler can execute calls, jumps, and other changes of flow and
will generate software interrupts and faults using the current definition of
the lOT. (Note that on entry to the 8MI handler the lOT is not set to the reset
real mode value of 0:0.)
8) The SMI handler can go from real mode to protected mode and vice-versa.
Almost anything that can be done normally may be done during the SMI
service routine.
9) Data from 8MM memory is not cached.
10) If the location of SMM space is beyond 1 MByte, the value in CS will
truncate the segment above 16 bits. This would prohibit doing calls or
INTS from real mode without restoring the 32-bit features of the 486
because of the incorrect return address on the stack.
11) An undefined opcode exception will typically be generated when
conditions are not correct to permit the execution of SMM instructions.
12) To execute outside the SMM region (BIOS, debugger, etc.) the C8 limit
must be changed after entry to the SMI handler. The limit of the CS
segment register is set to the size of the SMM region in AAR4. This means
that EIP cannot become larger than the SMM region size. Since jumps in
real mode do not change the C8 limit, this has implications for software
interrupts and jumps out of 8MM space. (See Section A.15 for details and
options.
13) Segment registers other than the CS have the limits set in the
non-programmer-visible portion that were present before the SM!. To
avoid a protection error due to limit or other violation, the RSOC SMM
instruction should be used to change the limit of the register in use. (See
Section A.14.)
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