TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
Initiating and Maintaining Pipelined Cycles
Pipelined addressing is always initiated by asserting NA during a
non-pipelined bus cycle with at least one wait state. For the first bus cycle
following RESET, an idle bus, or a hold acknowledge state is always
non-pipelined. Therefore, the TI486SLC/E always issues at least one
non-pipelined bus cycle following RESET, idle, or hold acknowledge before
pipelined addressing takes effect.
Once a bus cycle is in progress and the current address has been valid for one
entire bus state, the NA input is sampled at the end of every phase one until
the bus cycle is acknowledged. Once NA is sampled active, the TI486SLC/E
microprocessor is free to drive a new address and bus cycle definition on the
bus as early as the next bus state and as late as the last bus state in the cycle.
Figure 3-10 illustrates the fastest transition possible to pipelined addressing
following an idle bus state. In Cycle 1, NA is driven during state T2. Thus, Cycle
1 makes the transition to pipelined address timing, since it begins with T1 but
ends with T2P. Because the address for Cycle 2 is available before Cycle 2
begins, Cycle 2 is called a pipelined bus cycle, and it begins with a T1 P state.
Cycle 2 begins as soon as READY asserted terminates Cycle 1.
Figure 3-10. Fastest Transition to Pipelined Address Following Idle Bus State
CLK2
Idle ,
.~
,
, T1
Cycle 1
Non-Pipelined
(Write)
.
(Read)
Cycle 2
Pipelined ,
,
,.. ., ..
T1P , T2P :
Cycle 3
Pipelined ,
(Write) ,
., ..
, ,
, T2P , T1P
Cycle 4
Pipelined
(Read)
, Idle
,
.r-
A23-A1 _
BHE, BLs
MIlO, OIC ~~~~~--~-"""'~-...,....--~----r--~i'---.,......-"""'~~~~~~~~
iA@
,
LOCK ~~~~_~_va_l_id~I __ ~~_va~il_id_2_~~_~~~~lid_3_-+ __ ~_~~_-+~~~
, , ,
015-00 -L--.L.-<
Out 1
, ,-.~--~--~-
Note:
Following any idle bus state (Ti) the address is always non-pipelined and NA is sampled only during wait states. To start
address pipelining after an idle state requires a non-pipelined cycle with at least one wait state (Cycle 1 above). The
pipelined cycles (2, 3, and 4 above) are shown with various numbers of wait states.
3-27