TI486 Microprocessor - Al Kossow's Bitsavers

Overview
Table 4-2. Terminal Functions (Continued)
NAME
PIN
NO.
110 DESCRIPTION
BS16 C14 I Bus Size 16 (active low). This is an input that allows connection of the 32-bit TI4860LC/E
data bus to an external 16-bit data bus. When this input is activated, the microprocessor
performs multiple bus cycles to couple read and write accesses from devices that cannot
provide (accept) 32 bits of data in a single cycle. Ouring bus cycles with BS16 active, data
is transferred using data bus signals 015-00 only.
BUSY B9 I Coprocessor Busy (active low). This is an input from the coprocessor that indicates to
the TI4860LC/E that the coprocessor is currently executing an instruction and is not yet
able to accept another opcode. When the TI4860LC/E processor encounters a WAIT
instruction or any coprocessor instruction that operates on the coprocessor stack (Le.,
load, pop, arithmetic operation), BUSY is sampled. BUSY is continually sampled and
must be recognized as inactive before the CPU will supply the coprocessor with another
instruction. However, the following coprocessor instructions are allowed to execute even
if BUSY is active since these instructions are used for coprocessor initialization and
exception clearing: FNINIT, FNCLEX.
BUSY is internally connected to a pullup resistor to prevent it from floating active when
left unconnected.
CLK2 F12 I 2X Clock Input (active high). This signal is the basic timing reference for the
TI486DLC/E microprocessor. The CLK2 input is internally divided by two to generate the
internal processor clock. The external CLK2 is synchronized to a known phase of the
internal processor clock by the falling edge of the RESET signal. External timing
parameters are defined with respect to the rising edge of CLK2.
00 H12
01 H13
02 H14
03 J14
04 K14
05 K13
D6 L14
07 K12
08 L13
09 N14
010 M12
011 N13
012 N12
013 P13
014 P12
015 M11
016 N11
017 N10
018 P11
019 P10
020 M9
021 N9
022 P9
023 N8
024 P7
025 N6
026 P5
027 N5
028 M6
029 P4
030 P3
031 M5
I/O/Z
Data Bus (active high). The Data Bus (031-00) signals are 3-state bidirectional signals
that provide the data path between the TI4860LC/E and external memory and 1/0
devices. The data bus inputs data during memory read, 1/0 read and interrupt
acknowledge cycles and outputs data during memory and 1/0 write cycles. Oata read
operations require that specified data setup and hold times be met for correct operation.
The data bus signals are high active and float while the CPU is in a hold acknowledge
or float state.
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