TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
4.2.3 Bus Cycles Using BS16
Assertion of B816 during a bus cycle effectively changes the T14860LC/E
32-bit bus into a 16-bit data bus. Although slower, the 16-bit data bus usually
requires less hardware interface circuitry and generally offers greater
compatibility with 16-bit devices.
Non-Pipelined Cycles
With B816 asserted, all operand transfers physically occur on data bus lines
015-00. With B816 asserted during a 32-bit non-pipelined read or write,
additional bus cycles are issued by the CPU to transfer the data.
For data reads with only the two upper bytes selected (BE3 and/or BE2
asserted), data is read from 015-00.
For data writes with only the two upper bytes selected (BE3 and/or BE2
asserted), data is duplicated on 015-00 and no further action is required.
For data reads with all four bytes selected (at least BE1, BE2 asserted and
possibly BEO and/or BE3 also asserted), the CPU performs two 16-bit read
cycles using data lines 015-00. Lines 031-0'16 are ignored.
Oata writes with all four bytes selected (at least BE1, BE2 asserted and
possibly BEO and/or BE3 also asserted), the CPU performs two 16-bit write
cycles using data lines 015-00. Bytes 0 and 1 (corresponding to BEO, BE1)
are sent on the first bus cycle and bytes 2 and 3 (corresponding to BE2, BE3)
are sent on the second bus cycle. BEO and BE1 are always negated during
the second 16-bit bus cycle. Figure 4-13 illustrates two non-pipelined bus
cycles using B816.
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