TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
LOCK is activated on the CLK2 edge that begins the first locked bus cycle and
is deactivated when READY is returned at the end of the last locked bus cycle.
When using non-pipelined addressing, LOCK is asserted during phase 1 of
T1. When using pipelined addressing, LOCK is driven valid during phase 1 of
T1P.
Figure 4-4 through Figure 4-6 and Figure 4-13 illustrate LOCK timing during
non-pipelined cycles and Figure 4-8 through Figure 4-11 and Figure 4-14
cover the pipelined address case.
4.2.5 Interrupt Acknowledge (INTA) Cycles
The TI486DLC/E microprocessor is interrupted by an external source via an
input request on the INTR input (when interrupts are enabled). The
TI486DLC/E microprocessor responds with two locked interrupt acknowledge
cycles. These bus cycles are similar to read cycles. Each cycle is terminated
by READY sampled active as shown in Figure 4-15.
Figure 4-15. Interrupt Acknowledge Cycles
Idle
I
I
.~
Interrupt
Acknowledge
Cycle 1
Idle
(4 Bus States)
Interrupt
Acknowledge
Cycle 2
I Idle
I
.~
I T2 I T2 :
I T2 I T2 :
CLK2
BS16~~~~~~~~~~~~~~~~~~~~~~I--~~~
I
REAOY ~~~~~~~'---~~~~~~~~~~~~~~~~r-T'~ __ ~~
I
I I I Ignored I I I I I I Vector
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