TI486 Microprocessor - Al Kossow's Bitsavers

Clock Count Summary
7.4 Clock Count Summary
7.4.1 Assumptions
The following assumptions have been made in presenting the clock count
values for the individual instructions.
1) The instruction has been prefetched, decoded and is ready for execution.
2) Bus cycles do not require wait states.
3) There are no local bus HOLD requests delaying processor access to the
bus.
4) No exceptions are detected during instruction execution.
5) If an effective address is calculated, it does not use two general register
components. One register, scaling and displacement can be used within
the clock count shown. However, if the effective address calculation uses
two general register components, add 1 clock to the clock count shown.
6) All clock counts assume aligned 16-bit memory/IO operands for cache
miss counts.
7) If instructions access a misaligned 16-bit operand or a 32-bit operand on
even addresses, add 2 clocks for read or write, and add 4 clock counts for
read and write.
8) If instructions access a 32-bit operand on odd addresses, add 4 clocks for
read or write, and add 8 clocks for read and write.
7.4.2 Abbreviations
Table 7-16. Clock Count Abbreviations
The clock counts listed in the Instruction Set Summary Table are grouped by
operating mode and whether there is a register/cache hit or a cache miss. In
some cases, more than one clock count is shown in a column for a given
instruction, or a variable is used in the clock count. The abbreviations used for
these conditions are listed in Table 7-16.
CLOCK COUNT
SYMBOL
EXPLANATION
/ Register operand/memory operand
n
L
I
Number of times operation is repeated
Level of the stack frame
Condition jump taken I conditional jump not taken
\ CPL ::;; IOPL \ CPL > IOPL
7-13