TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
Non-Pipelined Wait States
Once a bus cycle begins, it continues until acknowledged by the external
system hardware using the TI486SLC/E READY input. Acknowledging the
bus cycle at the end of the first T2 results in the shortest possible bus cycle,
requiring only T1 and T2. If READY is not immediately asserted however, T2
states are repeated indefinitely until the READY input is sampled active. These
intermediate T2 states are referred to as wait states. If the external system
hardware is not able to receive or deliver data in two bus states, it withholds
the READY signal and at least one wait state is added to the bus cycle. Thus,
on an address-by-address basis the system is able to define how fast a bus
cycle completes.
Figure 3-6 illustrates non-pipelined bus cycles with one wait state added to
cycles 2 and 3. READY is sampled inactive at the end of the first T2 state in
cycles 2 and 3. Therefore, the T2 state is repeated until READY is sampled
active at the end of the second T2 and the cycle is then terminated. The
TI486SLC/E ignores the READY input at the end of the T1 state.
Figure 3-6. Various Non-Pipelined Bus Cycles with Different Numbers of Wait States
CLK2
I I Cycle 1 I Cycle 2 I I Cycle 3 I
I Idle I Non-Pipelined I Non-Pipelined I Idle I Non-Pipelined I Idle
I I (Read) I (Write) I I (Read) I
I I I I I I
I Ti I T1 I T1 T2 T2 I Ti I T1 T2 T2 I Ti
A23-A1, ~/--...I.-----" ----'--....I:~-~(8