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TI486 Microprocessor - Al Kossow's Bitsavers

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Register Set<br />

Figure 2-9. Gate Descriptor<br />

Call Gate descriptors are used to enter a procedure (subroutine) that executes<br />

at the same or a more privileged level. A Call Gate descriptor primarily defines<br />

the procedure entry point and the procedure's privilege level.<br />

31 16 15 14 13 12 11 8 7 o<br />

OFFSET 31-16 P DPL 0 TYPE 0 0 0 PARAMETERS +4<br />

SELECTOR 15-0 OFFSET 15-0 +0<br />

Table 2-7. Gate Descriptor Bit Definitions<br />

BIT<br />

POSITION<br />

MEMORY<br />

OFFSET<br />

NAME<br />

DESCRIPTION<br />

31-16 +4 OFFSET Offset used during a call gate to calculate the branch target.<br />

15-0 +0<br />

31-16 +0 SELECTOR Segment selector used during a call gate to calculate the branch target.<br />

15 +4 P Segment present<br />

14-13 +4 DPL Descriptor privilege level<br />

11-8 +4 TYPE Segment type:<br />

0100=16-bit call gate<br />

0101 =tack gate<br />

0110=16-bit interrupt gate<br />

0111 =16-bit trap gate<br />

11 00=32-bit call gate<br />

1110=32-bit interrupt gate<br />

1111 =32-bit trap gate<br />

4-0 +4 Parameters Number of 32-bit parameters to copy from the caller's stack to the called<br />

procedure's stack.<br />

2.3.2.3 Task Register<br />

The Task Register (TR) holds a 16-bit selector for the current Task State<br />

Segment (TSS) table as shown in Figure 2-10. The TR is loaded and stored<br />

via the L TR and STR instructions, respectively. The TR can be accessed only<br />

during protected mode and can be loaded only when the privilege level is 0<br />

(most privileged).<br />

Figure 2-10. Task Register<br />

15 o<br />

SELECTOR<br />

When the TR is loaded, the TR selector field indexes a TSS descriptor that<br />

must reside in the global descriptor table (GDT). The contents of the selected<br />

descriptor are cached on-chip in the hidden portion of the TR.<br />

2-24<br />

Programming Interface

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