TI486 Microprocessor - Al Kossow's Bitsavers

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Functional Timing 4.2 Functional Timing 4.2.1 Reset Timing and Internal Clock Synchronization RESET is the highest priority input signal and is capable of interrupting any processor activity when it is asserted. When RESET is asserted, the TI486DLC/E aborts any bus cycle. Idle, hold acknowledge, and suspend states are also discontinued and the reset state is established. RESET is used when the TI486DLC/E microprocessor is powered up to initialize the CPU to a known valid state and to synchronize the internal CPU clock with external clocks. RESET must be asserted for at least 15 CLK2 periods to ensure recognition by the TI486DLC/E microprocessor. If the self-test feature is to be invoked, RESET must be asserted for at least 80 CLK2 periods. RESET pulses less than 15 CLK2 periods may not have sufficient time to propagate throughout the TI486DLC/E and may not be recognized. RESET pulses less than 80 CLK2 periods followed by a self-test request may incorrectly report a self-test failure when no true failure exists. Provided the RESET falling edge meets specified setup and hold times, the internal processor clock phase is synchronized as illustrated in Figure 4-2. The internal processor clock is half the frequency of the CLK2 input and each CLK2 cycle corresponds to an internal CPU clock phase. Phase 2 of the internal clock is defined to be the second rising edge of CLK2 following the falling edge of RESET. Following the falling edge of REST (and after self-test if it was requested), the TI486DLC/E microprocessor performs an internal initialization sequence for approximately 400 CLK2 periods. The TI486DLC/E self-test feature is invoked if the BUSY input is in an active-low state when RESET falls inactive. The self-test sequence requires approximately (2 20 + 60) CLK2 periods to complete. Even if the self-test indicates a problem, the TI486DLC/E microprocessor attempts to proceed with the reset sequence. Figure 4-3 illustrates the bus activity and timing during the TI486DLC/E reset sequence. Upon completion of self-test, the EAX register contains 0000 OOOOh if the TI486DLC/E microprocessor passed its internal self-test with no problems detected. Any non-zero value in the EAX register indicates that the microprocessor is faulty. Figure 4-2. Internal Processor Clock Synchronization CLK2 RESET :1 '\~~~ 2 or 1 2 or 1 2 I I I I I I __-+__________ ~ ________ ~: __________ ~: __ __ - I I I I I INTERNAL ~ ~II .....___.....,V ll PROCESSOR, I : \ CLOCK ' I I 4-17
Functional Timing Figure 4-3. Bus Activity from RESET until First Code Fetch ~ Reset .,. , ;::: 15 CLK2 duration if not , I going to request self-test. I I ;::: 80 CLK2 duration before I requesting self-test. CLK2~ RESET ~ i~' ; CLK --v-V--v-v-v-i. (Internal) ~ I ( Internal ~ Cycle 1 Initialization Non-Plpehned 1 If self-test 2 is performed, add I, (Read) 20 20 + 60* to these numbers T1 T2 3nnru~' * Approximately \ ________________ ~I----~I - 1 21 1 1 21 1 1 2 1 2 I 11 2 I ~rtV1\.- , I BUSY ~. L--------.J. \ High for no Self-Test (see Note) \~~ ~ Low to Begin Self Test ~ ERROR~ ~~ ~ ~ BE3-BEO, WlR, Low IV ; MilO, HLDA ~ SS '/; '/; 1- Valid Up to 30 CLK2 ~ A31-A2 ~YI '/; '/; '/; Ie ; DIG, LOCK ~ I High i \ Valid A20M, BS16, Up to 30 CLK2 ~ '/; '/; ') I I ADS~Hi9h ~ I I I RXXXXXXXXXXI~ FLUSH,KEN,NA, ~ ~ READY, SUSP D31-DO ~--~s------ (Floating) ·----S~-----S~-I----r- I I SUSPA ~--~s------ (Floating) .---_s~----_s~-:---+-- I I Note: BUSY should be held stable for 80 CLK2 periods before and after the CLK2 period in which RESET falling edge occurs. 4.2.2 Bus Operation The TI486DLC/E microprocessor communicates with the external system through separate, parallel buses for data and address. This is commonly called a demultiplexed address/data bus. This demultiplexed bus eliminates the need for address latches required in multiplexed address/data bus configurations where the address and data are presented on the same pins at different times. TI486DLC/E instructions can act on memory data operands consisting of 8-bit bytes, 16-bit words or 32-bit double words. The TI486DLC/E bus architecture allows for bus transfers of these operands without restrictions on physical address alignment. Any byte boundary may require more than one bus cycle to transfer the operand. This feature is transparent to the programmer. 4-18 TI486DLCIE Bus Interface
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Page 112 and 113: Functional Timing Figure 3-3. Bus A
Page 114 and 115: Functional Timing 3.2.2.1 Bus Cycle
Page 116 and 117: Functional Timing Non-Pipelined Wai
Page 118 and 119: Functional Timing Because of the de
Page 120 and 121: Functional Timing Pipelined Wait St
Page 122 and 123: Functional Timing Initiating and Ma
Page 124 and 125: Functional Timing Figure 3-12. Comp
Page 126 and 127: Functional Timing Figure 3-13. Inte
Page 128 and 129: Functional Timing Shutdown Indicati
Page 130 and 131: Functional Timing Figure 3-17. Pipe
Page 132 and 133: Functional Timing As shown in Figur
Page 134 and 135: Functional Timing Figure 3-19. Requ
Page 138 and 139: Functional Timing Figure 3-22. 8MI
Page 140 and 141: Functional Timing HALT Initiated Su
Page 142 and 143: Functional Timing 3.2.12 Float Figu
Page 144 and 145: TI486DLC/E Bus Interface 4-1
Page 146 and 147: Chapter 4 TI486DLC/E Bus Interface
Page 148 and 149: Overview Table 4-1. TI486DLCIE SIgn
Page 150 and 151: Overview Table 4-2. Terminal Functi
Page 156 and 157: Overview Table 4-6. Signal States D
Page 158 and 159: Overview 4.1.2 Power Management 4.1
Page 162 and 163: Functional Timing The TI486DLC/E da
Page 164 and 165: Functional Timing Non-Pipelined Rea
Page 166 and 167: Functional Timing Initiating and Ma
Page 168 and 169: Functional Timing Figure 4-8. Faste
Page 170 and 171: Functional Timing Figure 4-9. Vario
Page 172 and 173: Functional Timing Once a pipelined
Page 174 and 175: Functional Timing 4.2.3 Bus Cycles
Page 176 and 177: Functional Timing Pipelined Cycles
Page 178 and 179: Functional Timing LOCK is activated
Page 180 and 181: Functional Timing 4.2.6 Halt and Sh
Page 182 and 183: Functional Timing Figure 4-17. Pipe
Page 184 and 185: Functional Timing Figure 4-19. Non-
Page 186 and 187: Functional Timing The TI486DLC/E sa
Page 188 and 189: Functional Timing 4.2.9 Hold Acknow
Page 192 and 193: Functional Timing 4.2.10 Coprocesso
Page 194 and 195: Functional Timing 4.2.12 Power Mana
Page 196 and 197: Functional Timing Stopping the Inpu
Page 198 and 199: Electrical Specifications 5-1
Page 200 and 201: Chapter 5 Electrical Specifications
Page 202 and 203: ElectricalConnecnons It is recommen
Page 204 and 205: Recommended Operating Conditions 5.
Page 206 and 207: DC Electrical Characteristics Table
Page 208 and 209: AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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AC Characteristics Figure 5-10. TI4
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AC Characteristics Figure 5-12. TI4
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Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
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Pin Assignments Table 6-1. TI486SLC
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Pin Assignments Figure 6-3. TI486DL
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Package Dimensions 6.2 Package Dime
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Thermal Characteristics 6.3 Thermal
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Instruction Set 7-1
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Chapter 7 Instruction Set This sect
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Instruction Fields 7.2 Instruction
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Instruction Fields 7.2.5 reg Field
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Instruction Fields Table 7-7. mod r
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Instruction Fields 7.2.11 sreg3 Fie
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Clock Count Summary 7.4 Clock Count
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--- --;.J -L 01 Table 7-17. Instruc
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I . ~ -.....J Table 7-17. Instructi
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Table 7-17. Instructions, Opcodes,
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-....J N (J.) Table 7-17. Instructi
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I I i I i Table 7-17. Instructions,
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...... ...... '" Table 7-17. Instru
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-....J N co Table 7-17. Instruction
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"-.I ~ Table 7-17. Instructions, Op
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U Appendix A TI486 SMM Pro rammer's
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SMM Implementation A.2 SMM Implemen
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Figure A-1. SMM Memory Space Header
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SMM Implementation 6) NMI is the on
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Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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i**********************************
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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