TI486 Microprocessor - Al Kossow's Bitsavers

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System Management Mode The new SMM instructions, listed in Table 2-24, can be executed only if: (a) the Current Privilege Level (CPL) = 0 and the SMAC bit (CCR1, bit 2) is set; or (b) CPL =0 and the CPU is in an 8MI service routine (SMI = 0). If both these conditions are not met and an attempt is made to execute an SVDC, RSDC, SVLDT, RSLDT, SVTS, RST8, or R8M instruction, an invalid opcode exception is generated. These instructions can be· executed outside of defined SMM space provided the above conditions are met. All of the SMM instructions (except RSM) save or restore 80 bits of data, allowing the saved values to include the hidden portion of the register contents. Table 2-24. SMM Instruction Set INSTRUCTION OPCODE FORMAT DESCRIPTION SVDC OF 78 [mod sreg3 rim] SVDC mem80, sreg3 Save Segment Register and Descriptor Saves reg DS, ES, FS, GS, or SS to mem80. RSDC OF 79 [mod sreg3 rim] RSDC sreg3, mem80 Restore Segment Register and Descriptor Restores reg DS, ES, FS, GS, or SS from mem80. (eS is automatically restored with RSM) SVLDT OF 7A [mod 000 rim] SVLDTmem80 Save LDTR and Descriptor Saves Local Descriptor Table (LDTR) to mem80. RSLDT OF 78 [mod 000 rim] RSLDTmem80 Restore LDTR and Descriptor Restores Local Descriptor Table (LDTR) from mem80. SVTS OF 7C [mod 000 rim] SVTS mem80 Save TSR and Descriptor Save Task State Register (TSR) to mem80. RSTS OF 7D [mod 000 rim] RSTS mem80 Restore TSR and Descriptor Restores Task State Register (TSR) from mem80. RSM OFAA RSM Resume Normal Mode Exits SMM mode. The CPU state is restored using the SMM memory space header and execution resumes at interrupted point. Note: mem80 = 80-bit memory location. 2.6.5 SMM Memory Space SMM memory space is defined by assigning Address Region 4 to SMM memory space. This assignment is made by setting bit 7 (SM4) in the on-chip CCR1 register. ARR4, also an on-chip configuration register, specifies the base address and size of the SMM memory space. The base address must be a multiple of the SMM memory space size. For example, a 32 KByte SMM memory space must be located at a 32 KByte address boundary. The memory space size can range from 4 KBytes to 16 MBytes. SMM memory space accesses can use address pipelining, and are always non-cacheable. SMM accesses ignore the state of the A20M input pin and drive the A20 address bit to the unmasked value. Access to the SMM memory space can be made while not in SMM mode by setting the System Management Access (SMAC) bit in the CCR 1 register. This feature may be used to initialize the 8MM memory space. 2-55
System Management Mode While in SMM mode, SMADS address strobes are generated instead of ADS for SMM memory accesses. Any memory accesses outside the defined SMM space result in normal memory accesses and ADS strobes. Data (non-code) accesses to main memory that overlap with defined SMM memory space are allowed if bit 3 in CCR1 (MMAC) is set. In this case, ADS strobes are generated for data accesses only and SMADS strobes continue to be generated for code accesses. 2.6.6 SMI Service Routine Execution Upon entry into SMM after the SMM header has been saved, the CRO, EFLAGS, and DR? registers are set to their reset values. The Code Segment (CS) register is loaded with the base and limits defined by the ARR4 register and the SMI service routine begins execution at the SMM base address in real mode. The programmer must then save the value of any registers that may be changed by the SMI service routine. For data accesses immediately after entering the SMI service routine, the programmer must use CS as a segment override. I/O port access is possible during the routine but care must be taken to save registers modified by the I/O instructions. Before using a segment register, the register's descriptor cache contents should be saved using the SVDC instruction. While executing in the SMM space, execution flow can transfer to normal memory locations. Hardware interrupts (INTRs and NMls) may be serviced during an SMI service routine. If interrupts are to be serviced while operating in the SMM memory space, the SMM memory space must be within the 0 to 1 MByte address range to guarantee proper return to the SMI service routine after handling the interrupt. INTRs are automatically disabled when entering SMM since the IF flag is set to its reset value. However, NMls remain enabled. If it is desired to disable NMI, it should be done immediately after entering the SMI service routine by the system hardware logic. Within the SMI service routine, protected mode may be entered and exited as required, and real or protected mode device drivers can be called. To exit the SMI service routine, a Resume (RSM) instruction, rather than an IRET, is executed. The RSM instruction causes the TI486 to restore the CPU state using the SMM header information and resume execution at the interrupted point. If the full CPU state was saved by the programmer, the stored values should be reloaded prior to executing the RSM instruction using the MOV and the RSDC, RSLDT, and RSTS instructions. CPU States Related to SMM and Suspend Mode The state diagram shown in Figure 2-31 illustrates the various CPU states associated with SMM and suspend mode. While in the SMI service routine, the TI486 can enter suspend mode either by (1) executing a HALT instruction or (2) by asserting the SUSP input. 2-56 Programming Interface
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
Page 38 and 39: Processor Initialization Table 2-1.
Page 40 and 41: Instruction Set Overview 2.2 Instru
Page 42 and 43: Register Set 2.3 Register Set There
Page 44 and 45: Register Set Pointer and Index Regi
Page 46 and 47: Register Set 2.3.1.2 Segment Regist
Page 48 and 49: Register Set 2.3.1.3 Instruction Po
Page 50 and 51: Register Set 2.3.2 System Register
Page 52 and 53: Register Set 2.3.2.1 Control Regist
Page 54 and 55: Register Set 2.3.2.2 Descriptor Tab
Page 56 and 57: Register Set Table 2-6. Segment Des
Page 58 and 59: Register Set During task switching,
Page 60 and 61: Register Set The CCRO register (Tab
Page 62 and 63: Register Set Table 2-9. TI486DLCIE
Page 64 and 65: Register Set Table 2-12. ARR 1-ARR4
Page 66 and 67: Register Set 2.3.2.6 Test Registers
Page 68 and 69: Register Set Table 2-14. TR6 and TR
Page 70 and 71: Address Spaces 2.4 Address Spaces T
Page 72 and 73: Address Spaces 2.4.2 Memory Address
Page 74 and 75: Address Spaces Figure 2-21. Real Mo
Page 76 and 77: Address Spaces Figure 2-24. Paging
Page 78 and 79: Interrupts and Exceptions 2.5 Inter
Page 80 and 81: Interrupts and Exceptions 2.5.3 Int
Page 82 and 83: Interrupts and Exceptions Table 2-2
Page 84 and 85: System Management Mode 2.6 System M
Page 86 and 87: System Management Mode Figure 2-29.
Page 90 and 91: System Management Mode During SMM o
Page 92 and 93: Protection The Current Privilege Le
Page 94 and 95: Virtual 8086 Mode 2.9 Virtual 8086
Page 96 and 97: TI486SLC/E Bus Interface 3-1
Page 98 and 99: Chapter 3 TI486SLC/E Bus Interface
Page 100 and 101: Overview Table 3-1. TI486SLCIE Sign
Page 102 and 103: Overview Table 3-2. Terminal Functi
Page 108 and 109: Overview 3.1.1 Bus Cycle Definition
Page 110 and 111: Overview Table 3-5 shows the state
Page 112 and 113: Functional Timing Figure 3-3. Bus A
Page 114 and 115: Functional Timing 3.2.2.1 Bus Cycle
Page 116 and 117: Functional Timing Non-Pipelined Wai
Page 118 and 119: Functional Timing Because of the de
Page 120 and 121: Functional Timing Pipelined Wait St
Page 122 and 123: Functional Timing Initiating and Ma
Page 124 and 125: Functional Timing Figure 3-12. Comp
Page 126 and 127: Functional Timing Figure 3-13. Inte
Page 128 and 129: Functional Timing Shutdown Indicati
Page 130 and 131: Functional Timing Figure 3-17. Pipe
Page 132 and 133: Functional Timing As shown in Figur
Page 134 and 135: Functional Timing Figure 3-19. Requ
Page 136 and 137: Functional Timing Figure 3-21. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-2. Terminal Functi
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing Figure 4-23. Requ
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
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DC Electrical Characteristics Table
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AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
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Pin Assignments Table 6-1. TI486SLC
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Pin Assignments Figure 6-3. TI486DL
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Package Dimensions 6.2 Package Dime
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Thermal Characteristics 6.3 Thermal
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Instruction Set 7-1
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Chapter 7 Instruction Set This sect
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Instruction Fields 7.2 Instruction
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Instruction Fields 7.2.5 reg Field
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Instruction Fields Table 7-7. mod r
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Instruction Fields 7.2.11 sreg3 Fie
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Clock Count Summary 7.4 Clock Count
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--- --;.J -L 01 Table 7-17. Instruc
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I . ~ -.....J Table 7-17. Instructi
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Table 7-17. Instructions, Opcodes,
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-....J N (J.) Table 7-17. Instructi
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I I i I i Table 7-17. Instructions,
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...... ...... '" Table 7-17. Instru
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-....J N co Table 7-17. Instruction
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"-.I ~ Table 7-17. Instructions, Op
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U Appendix A TI486 SMM Pro rammer's
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SMM Implementation A.2 SMM Implemen
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Figure A-1. SMM Memory Space Header
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SMM Implementation 6) NMI is the on
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Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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i**********************************
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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