TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
The TI486DLC/E data bus (D31-DO) is a bidirectional bus that can be
configured as either a 16-bit or 32-bit wide bus as determined by 8816. The
bus is 16 bits wide when 8816 is asserted. When 32 bits wide, memory and
liD spaces are physically addressed as arrays of 32-bit double words. The
TI486DLC/E drives the data bus during write bus cycles, and the external
system hardware drives the data bus during read bus cycles.
Every bus cycle begins with the assertion of the address strobe (ADS). ADS
indicates that the TI486DLC/E has issued a new address and new bus cycle
definition signals. A bus cycle is defined by four signals: MilO, WiR, Die and
LOCK. MilO defines if a memory or I/O operation is occurring, wlFi.. defines the
cycle to be read or write, and Die indicates whether a data or control cycle is
in effect. LOCK indicates that the current cycle is a locked bus cycle. Every bus
cycle completes when the system hardware returns READY asserted.
The TI486DLC/E performs the following bus cycle types:
• Memory read
• Locked memory read
• Memory write
• Locked memory write
• liD read (or coprocessor read)
• liD write (or coprocessor write)
• Interrupt acknowledge (always locked)
• Halt/shutdown
When the TI486DLC/E microprocessor has no pending bus requests, the bus
enters the idle state. There is no encoding of the idle state on the bus cycle
definition signals; however, the idle state can be identified by the absence of
further assertions of ADS following a completed bus cycle.
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