TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
3.2.12 Float
Figure 3-27. Entering and Exiting Float
Activating the FL T input floats all TI486SLC/E microprocessor bidirectional
and output signals. Asserting FLT electrically isolates the TI486SLC/E
microprocessor from the surrounding circuitry. This feature is useful in
board-level test environments. As the TI486SLC/E microprocessor is
packaged in a surface mount PQFP, it is not usually socketed and cannot be
removed from the motherboard when In-Circuit Emulation (ICE) is needed.
Float capability allows connection of an emulator by clamping the emulator
probe onto the TI486SLC/E microprocessor PQFP without removing it from
the circuit board.
FLT is an asynchronous, active-low input. It is recognized on the rising edge
of CLK2. When recognized, it aborts the current bus state and floats the
outputs of the TI486SLC/E microprocessor as shown in Figure 3-27. FLT
must be asserted for a minimum of 16 CLK2 cycles. To exit the float condition,
RESET should be asserted and held asserted until after FLT is deasserted.
Asserting the FLT input unconditionally aborts the current bus cycle and forces
the TI486SLC/E microprocessor into the float mode. As a result, the
TI486SLC/E microprocessor is not guaranteed to enter float in a valid state.
After deactivating FLT, the TI486SLC/E CPU is not guaranteed to exit float in
a valid state. The TI486SLC/E microprocessor RESET input must be asserted
prior to exiting float to guarantee that the TI486SLC/E is reset and that it
returns in a valid state.
CLK2
FLT \ ,
CONTROL ~ Valid
DATA -{}--{ Valid
}-------------------{'--____...I X '-___
}------------------('-____ ......IC
ADDRESS ~ Valid }------------------{'-__...I X '-___
RESET
------------------,
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