TI486 Microprocessor - Al Kossow's Bitsavers

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Table 7-17. Instructions, Opcodes, Flags, and Clock Summary (Continued) FLAGS I REAL MODE PROTECTED CLOCKS MODE CLOCKS INSTRUCTION OPCODE 0 REGI REG! D I T S Z A P C CACHE F CACHE CACHE F F F F F F F F MISS HIT HIT NOTES CACHE READ PROTECTED MISS MODE MODE JLElJNG Jump on Less or EquallNot Greater u u u u u u u u u 8 8-Bit displacement 7E:t: 411 611 Full displacement OF 8El1 411 611 JMP Unconditional Jump u u u u u u u u u 1 2,6,7,8 Short EB:t: 4 6 Direct within Segment E911 4 6 Register/Memory Indirect within Segment FF [mod 100 rIm] 6/8 10 6/8 10 Direct Intersegment EA [full offset, selector] 9 26 Call Gate Same Privilege Level 45 45 16-Bit Task to 16-bit TSS 265 266 16-Bit Task to 32-bit TSS 296 320 16-Bit Task to V86 Task 182 209 32-Bit Task to 16-bit TSS 241 261 32-Bit Task to 32-bit TSS 299 343 32-Bit Task to V86 Task 185 232 -....J N ...... Indirect Intersegment FF [mod 101 rIm] 11 14 30 30 Call Gate Same Privilege Level 47 47 16-Bit Task to 16-bit TSS 270 271 16-Bit Task to 32-bit TSS 301 325 16-Bit Task to V86 Task 184 214 32-Bit Task to 16-bit TSS 246 268 32-Bit Task to 32-bit TSS 304 348 32-Bit Task to V86 Task 187 237 JNB/JAElJNC Jump on Not Belowl u u u u u u u u u 8 Above or EquaVNot Carry 8-Bit displacement 73:t: 411 611 Full displacement OF 8311 411 611 t = immediate data :t: = 8-bit displacement § = 16-bit displacement 11 = 32-bit displacement m = Flag modified u = Flag unchanged Notes: 1) Exception 13 fault (general protection) will occur in Read Mode if an operand reference is made that partially or fully extends beyond the maximum CS, OS, ES, FS, or GS segment limit (FFFFh). Exception 12 fault (stack segment limit violation or not present) will occur in Real Mode if an operand reference is made that partially or fully extends beyond the maximum SS limit. 2) Exception 13 fault will occur if the memory operand in CS, OS, ES, FS, or GS cannot be used due to either a segment limit violation or an access rights violation. If a stack limit is violated, an exception 12 occurs. 3) This is a Protected Mode instruction. Attempted execution in Real Mode will result in exception 6 (invalid opcode). 4) An exception may occur, depending on the value of the operand. 5) LOCK is asserted during descriptor table accesses. 6) <strong>Al</strong>l segment descriptor accesses in the GOT or LOT made by this instruction will automatically assert LOCK to maintain descriptor integrity in multiprocessor systems. 7) JMP, CALL, INT, RET, and IRET instructions referring to another code segment will cause an exception 13, if an applicable privilege rule is violated. 8) The destination of a JMP, CALL, INT, RET, or IRET must be in the defined limit of a code segment or an exception 13 fault will occur. Q ~ ~ ~ I ~
-....I N I\) Table 7-17. Instructions, Opcodes, Flags, and Clock Summary (Continued) INSTRUCTION OPCODE FLAGS 0 D I T S Z F F F F F F JNBElJA Jump on Not Below or Equal/Above u u u u u u 8-Bit displacement 77:j: Full displacement OF87~ A P C F F F u u u REAL MODE CLOCKS REG! CACHE HIT 411 411 CACHE MISS PROTECTED MODE CLOCKS REGI CACHE HIT 611 611 CACHE MISS NOTES READ PROTECTED MODE MODE 8 Q ~ ~ ~ en i -< JNElJNZ Jump on Not Equal/Not Zero u u u u u u 8-Bit Displacement 75:j: Full Displacement OF 85~ u u u 411 411 611 611 8 JNUJGE Jump on Not Less/Greater or Equal u u u u u u 8-Bit displacement 7D:j: Full displacement OF8D~ u u u 411 411 611 611 8 JNLElJG Jump on Not Less or Equal/Greater u u u u u u 8-Bit displacement 7F:j: Full displacement OF8F~ u u u 411 411 611 611 8 JNO Jump on Not Overflow u u u u u u 8-Bit displacement 71:j: Full displacement OF 81~ u u u 411 411 611 611 8 JNP/JPO Jump on Not Parity/Parity Odd u u u u u u 8-Bit displacement 7B:j: Full displacement OF8B~ u u u 411 411 611 611 8 JNS Jump on Not Sign u u u u u u 8-Bit displacement 79:j: Full displacement OF89~ u u u 411 411 611 611 8 JO Jump on Overflow u u u u u u 8-Bit displacement 70:j: Full displacement OF 80~ u u u 411 411 611 611 8 JP/JPE Jump on Parity/Parity Even u u u u u u 8-Bit displacement 7A:j: Full displacement OF8A~ u u u 411 411 611 611 8 s- CI) =t 5 ~ ~ JS Jump on Sign u u u u u u 8-Bit displacement 78:j: Full displacement OF 88~ u u u 411 411 611 611 8
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
Page 202 and 203: ElectricalConnecnons It is recommen
Page 204 and 205: Recommended Operating Conditions 5.
Page 206 and 207: DC Electrical Characteristics Table
Page 208 and 209: AC Characteristics Figure 5-2. TI48
Page 210 and 211: AC Characteristics Table 5-9. AC Ch
Page 212 and 213: AC Characteristics Table 5-11. AC C
Page 214 and 215: ____ AC Characteristics 5.5.3 RESET
Page 220 and 221: Mechanical Specifications 6-1
Page 222 and 223: Chapter 6 Mechanical Specifications
Page 224 and 225: Pin Assignments Table 6-1. TI486SLC
Page 226 and 227: Pin Assignments Figure 6-3. TI486DL
Page 228 and 229: Package Dimensions 6.2 Package Dime
Page 230 and 231: Thermal Characteristics 6.3 Thermal
Page 232 and 233: Instruction Set 7-1
Page 234 and 235: Chapter 7 Instruction Set This sect
Page 236 and 237: Instruction Fields 7.2 Instruction
Page 238 and 239: Instruction Fields 7.2.5 reg Field
Page 240 and 241: Instruction Fields Table 7-7. mod r
Page 242 and 243: Instruction Fields 7.2.11 sreg3 Fie
Page 244 and 245: Clock Count Summary 7.4 Clock Count
Page 246 and 247: --- --;.J -L 01 Table 7-17. Instruc
Page 248 and 249: I . ~ -.....J Table 7-17. Instructi
Page 250 and 251: Table 7-17. Instructions, Opcodes,
Page 254 and 255: -....J N (J.) Table 7-17. Instructi
Page 256 and 257: I I i I i Table 7-17. Instructions,
Page 258 and 259: ...... ...... '" Table 7-17. Instru
Page 260 and 261: -....J N co Table 7-17. Instruction
Page 262 and 263: "-.I ~ Table 7-17. Instructions, Op
Page 264 and 265: Table 7-17. Instructions, Opcodes,
Page 266 and 267: U Appendix A TI486 SMM Pro rammer's
Page 268 and 269: SMM Implementation A.2 SMM Implemen
Page 270 and 271: Figure A-1. SMM Memory Space Header
Page 272 and 273: SMM Implementation 6) NMI is the on
Page 274 and 275: Instruction Summary A.4 Instruction
Page 276 and 277: Instruction Summary A.4.3 Resume No
Page 278 and 279: Instruction Summary A.4.6 Save LDTR
Page 280 and 281: 8MI Handler Example A.5 SMI Handler
Page 282 and 283: 8MI Handler Example execute_halt: C
Page 284 and 285: 8MI Handler Example COMMENT A The T
Page 286 and 287: 8MI Handler Example arrl arr2 arr3
Page 288 and 289: .MODEL SMALL . STACK .386P INCLUDE
Page 290 and 291: Testing/Debugging SMM Code sgdt COM
Page 292 and 293: Testing/Debugging SMM Code i*******
Page 294 and 295: TI486 Power Management Features A.7
Page 296 and 297: Detection of Tl486 CPU A.9 Detectio
Page 298 and 299: Detection of SMM Capable Version A.
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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