TI486 Microprocessor - Al Kossow's Bitsavers

8MI Handler Example
;Determine Why Are We In The SMI Handler
COMMENT A
Chip set/Core logic unique instructions will follow. The chip set will be
used to deter.mine what caused the SMM interrupt to occur. The B~OS could also
"jump" to this point in the SMM region.
A
;
; Decision Tree:
;a)
;b)
;c)
If timer, go to timer_expired
If port i/o occurred to a trapped location, go to port_io_caused
If the cpu was turned off, go to cpu_turned_off
;timer_expired;
COMMENT A
A chip set timer has expired. Unique code would appear to deter.mine which
timer. Depending on the purpose of the timer the handler could;
1) Reduce the clock frequency
2) Execute a halt instruction and enter suspend mode
3) Turn current off to the CPU
4) Turn off a peripheral device
5) Reset the timer and increment a counter
reduce_clock:
COMMENT A
To go to a lower CPU current requirement the CPU clock can be reduced. The
CPU clock can be reduced from its current setting to a lower value. That
value could be zero. Since the CPU is a static device and will maintain the
state of all its registers in the absence of a clock input there is no state
saving requirement. ~t is assumed that by writing to the chip set it will
reduce or zero the clock. ~f the clock is stopped then the next instruction
to be executed will be one in this SM~ handler immediately following the
point where the chip set turned the clock off.
jmp end_timer:
A-16 Tl486 8MM Programmer's Guide