TI486 Microprocessor - Al Kossow's Bitsavers

Overview
Table 3-2. Terminal Functions (Continued)
NAME
PIN
NO.
I/O
DESCRIPTION
KEN 29 I Cache Enable (active low). This is an input which indicates that the data being returned
during the current cycle is cacheable. When KEN is active and the TI486SLC/E is
performing a cacheable code fetch or memory data read cycle, the cycle is transformed
into a cache fill. Use of the KEN input to control cacheability is optional. The
non-cacheable region registers can also be used to control cacheablity. Memory
addresses specified by the non-cacheable region registers are not cacheable regardless
of the state of KEN. 1/0 accesses, locked reads, SMM address space accesses, and
interrupt acknowledge cycles are never cached.
During cached code fetches, two contiguous read cycles are performed to completely
fill the 4-byte cache line. KEN must be asserted during both read cycles in order to cause
a cache line fill. During cached data reads, the TI486SLC/E performs only those bus
cycles necessary to supply the required data to complete the current operation. Valid bits
are maintained for each byte in the cache line, thus allowing data operands of less than
4 bytes to reside in the cache.
During any cache fill cycle with KEN asserted, the TI486SLC/E ignores the state of the
byte enables (BHE and BLE) and always writes two bytes of data into the cache. The
KEN input is ignored following reset and can be enabled using the KEN bit in the CCRD
configuration register.
KEN is internally connected to a pullup resistor to prevent it from floating active when left
unconnected.
LOCK 26 I LOCK (active low). LOCK is asserted to deny control of the CPU bus to other bus
masters. The LOCK signal may be explicitly activated during bus operations by including
the LOCK prefix on certain instructions. LOCK is always asserted during descriptor and
page table updates, interrupt acknowledge sequences and when executing the XCHG
instruction. The TI486SLC/E does not enter the hold acknowledge state in response to
HOLD while the LOCK input is active.
MilO 23 OIZ MemoryllO. This signal is low during 1/0 read and write cycles and is high during
memory cycles.
NA 6 I Next Address Request (active low). This is an input used to request address pipelining
by the system hardware. When asserted, the system indicates that it is prepared to
accept new bus cycle definition and address signals (MilO, DIG, W/R, A23-A 1, BHE, and
BLE) from the microprocessor even if the current bus cycle has not been terminated by
assertion of READY. If the TI486SLC/E has an internal bus request pending and the NA
input is sampled active, the next bus cycle definition and address signals are driven onto
the bus.
NC 27,45,46 - No connection. Should be left disconnected.
NMI 38 I Non-maskable Interrupt Request. This is a rising-edge-sensitive input that causes the
processor to suspend execution of the current instruction stream and begin execution
of an NMI interrupt service routine. The NMI interrupt service request cannot be masked
by software. Asserting NMI causes an interrupt which internally supplies interrupt vector
2h to the CPU core. External interrupt acknowledge cycles are not necessary since the
NMI interrupt vector is supplied internally.
The TI486SLC/E samples NMI at the beginning of each phase 2. To assure recognition,
NMI must be inactive for at least eight CLK2 periods and then be active for at least eight
CLK2 periods. Additionally, specified setup and hold times must be met to guarantee
recognition at a particular clock edge.
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