TI486 Microprocessor - Al Kossow's Bitsavers

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Pin Assignments Table 6-1. TI486SLCIE and TI486SLCIE- V Signal Names Sorted by Pin Number PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME 1 DO 21 Vee 41 Vss 61 A11 81 D15 2 Vss 22 Vss 42 ~ 62 A12 82 D14 3 HLDA 23 MilO 43 susP 63 Vss 83 D13 4 HOLD 24 DIG 44 SUSPA 64 A13 84 Vee 5 Yss 25 W/R 45 Ne 65 A14 85 Vss 6 NA 26 LOCK 46 Ne 66 A15 86 D12 7 READY 27 Ne 47 SMI 67 Vss 87 D11 8 Vee 28 FLT 48 Vee 68 Vss 88 D10 9 Vee 29 KEN 49 Vss 69 Vee 89 D9 10 Vee 30 FLUSH 50 VSS 70 A16 90 D8 11 Vss 31 A20M 51 A2 71 Vee 91 Vee 12 Vss 32 Vee 52 A3 72 A17 92 D7 13 Vss 33 RESET 53 A4 73 A18 93 D6 14 Vss 34 BUSY 54 A5 74 A19 94 D5 15 eLK2 35 ~ 55 A6 75 A20 95 D4 16 ADS 36 ERROR 56 A7 76 A21 96 D3 17 BLE 37 PEREQ 57 Vee 77 Vss 97 Vee 18 A1 38 NMI 58 A8 78 Vss 98 Vss 19 BHE 39 Vee 59 A9 79 A22 99 D2 20 SMADS 40 INTR 60 A10 80 A23 100 D1 Table 6-2. TI486SLCIE and TI486SLCIE-V Pin Numbers Sorted by Signal Name SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN NAME NO. NAME NO. NAME NO. NAME NO. NAME NO. A1 18 A21 76 D11 87 PEREQ 37 Vee 97 A2 51 A22 79 D12 86 READY 7 Vss 2 A3 52 A23 80 D13 83 RESET 33 Vss 5 A4 53 ADS 16 D14 82 SMADS 20 Vss 11 A5 54 A20M 31 D15 81 SMI 47 Vss 12 A6 55 BHE 19 DIG 24 susP 43 Vss 13 A7 56 BLE 17 ERROR 36 SUSPA 44 Vss 14 A8 58 BUSY 34 FLT 28 Vee 8 Vss 22 A9 59 eLK2 15 FLUSH 30 Vee 9 Vss 35 A10 60 DO 1 HOLD 4 Vee 10 Vss 41 A11 61 D1 100 HLDA 3 Vee 21 Vss 49 A12 62 D2 99 INTR 40 Vee 32 Vss 50 A13 64 D3 96 KEN 29 Vee 39 Vss 63 A14 65 D4 95 LOCK 26 Vee 42 Vss 67 A15 66 D5 94 MilO 23 Vee 48 Vss 68 A16 70 D6 93 NA 6 Vee 57 Vss 77 A17 72 D7 92 Ne 27 Vee 69 Vss 78 A18 73 D8 90 Ne 45 Vee 71 Vss 85 A19 74 D9 89 Ne 46 Vee 84 Vss 98 A20 75 D10 88 NMI 38 Vee 91 W/R 25 6-5
Pin Assignments The pin assignments for the TI486DLC/E and TI486DLC/E-V are shown as viewed from the pin side in Figure 6-2 and as viewed from the top side (component side when mounted on a PC board) in Figure 6-3. The signal names are listed in Table 6-3 and Table 6-4, sorted by pin number and signal name respectively. Figure 6-2. TI486DLCIE and TI486DLCIE-V Package Pins (Bottom View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 B Pin # 1 Index Mark (On Top Side) c D E F G H J K L M N p (G8888GGGG88GGG 888GG88888GGG8 G8GGG88G88GG8G 88G 8GG 888 888 888 8GG G8® 88G 888 (BOTTOM TI486DLC/E 8GG VIEW) 8S8 888 888 888 088 888 B8888888888888 8880S§S88GGG88 8GS8@GGGGGG8GG NC - No internal connection 6-6 Mechanical Specifications
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.TEXAS INSTRUMENTS TI486 Microproce
Page 4 and 5:
TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-21. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
Page 174 and 175: Functional Timing 4.2.3 Bus Cycles
Page 176 and 177: Functional Timing Pipelined Cycles
Page 178 and 179: Functional Timing LOCK is activated
Page 180 and 181: Functional Timing 4.2.6 Halt and Sh
Page 182 and 183: Functional Timing Figure 4-17. Pipe
Page 184 and 185: Functional Timing Figure 4-19. Non-
Page 186 and 187: Functional Timing The TI486DLC/E sa
Page 188 and 189: Functional Timing 4.2.9 Hold Acknow
Page 190 and 191: Functional Timing Figure 4-23. Requ
Page 192 and 193: Functional Timing 4.2.10 Coprocesso
Page 194 and 195: Functional Timing 4.2.12 Power Mana
Page 196 and 197: Functional Timing Stopping the Inpu
Page 198 and 199: Electrical Specifications 5-1
Page 200 and 201: Chapter 5 Electrical Specifications
Page 202 and 203: ElectricalConnecnons It is recommen
Page 204 and 205: Recommended Operating Conditions 5.
Page 206 and 207: DC Electrical Characteristics Table
Page 208 and 209: AC Characteristics Figure 5-2. TI48
Page 210 and 211: AC Characteristics Table 5-9. AC Ch
Page 212 and 213: AC Characteristics Table 5-11. AC C
Page 214 and 215: ____ AC Characteristics 5.5.3 RESET
Page 220 and 221: Mechanical Specifications 6-1
Page 222 and 223: Chapter 6 Mechanical Specifications
Page 226 and 227: Pin Assignments Figure 6-3. TI486DL
Page 228 and 229: Package Dimensions 6.2 Package Dime
Page 230 and 231: Thermal Characteristics 6.3 Thermal
Page 232 and 233: Instruction Set 7-1
Page 234 and 235: Chapter 7 Instruction Set This sect
Page 236 and 237: Instruction Fields 7.2 Instruction
Page 238 and 239: Instruction Fields 7.2.5 reg Field
Page 240 and 241: Instruction Fields Table 7-7. mod r
Page 242 and 243: Instruction Fields 7.2.11 sreg3 Fie
Page 244 and 245: Clock Count Summary 7.4 Clock Count
Page 246 and 247: --- --;.J -L 01 Table 7-17. Instruc
Page 248 and 249: I . ~ -.....J Table 7-17. Instructi
Page 250 and 251: Table 7-17. Instructions, Opcodes,
Page 254 and 255: -....J N (J.) Table 7-17. Instructi
Page 256 and 257: I I i I i Table 7-17. Instructions,
Page 258 and 259: ...... ...... '" Table 7-17. Instru
Page 260 and 261: -....J N co Table 7-17. Instruction
Page 262 and 263: "-.I ~ Table 7-17. Instructions, Op
Page 266 and 267: U Appendix A TI486 SMM Pro rammer's
Page 268 and 269: SMM Implementation A.2 SMM Implemen
Page 270 and 271: Figure A-1. SMM Memory Space Header
Page 272 and 273: SMM Implementation 6) NMI is the on
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Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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i**********************************
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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