TI486 Microprocessor - Al Kossow's Bitsavers

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Functional Timing
3.2 Functional Timing
3.2.1 Reset Timing and Internal Clock Synchronization
RESET is the highest priority input signal and is capable of interrupting any
processor activity when it is asserted. When RESET is asserted, the
TI486SLC/E aborts any bus cycle. Idle, hold acknowledge, and suspend
states are also discontinued and the reset state is established. RESET is used
when the TI486SLC/E microprocessor is powered up to initialize the CPU to
a known valid state and to synchronize the internal CPU clock with external
clocks.
RESET must be asserted for at least 15 CLK2 periods to ensure recognition
by the TI486SLC/E microprocessor. If the self-test feature is to be invoked,
RESET must be asserted for at least 80 CLK2 periods. RESET pulses less
than 15 CLK2 periods may not have sufficient time to propagate throughout
the TI486SLC/E and may not be recognized. RESET pulses less than 80 CLK2
periods followed by a self-test request may incorrectly report a self-test failure
when no true failure exists.
Provided the RESET falling edge meets specified setup and hold times, the
internal processor clock phase is synchronized as illustrated in Figure 3-2.
The internal processor clock is half the frequency of the CLK2 input and each
CLK2 cycle corresponds to an internal CPU clock phase. Phase 2 of the
internal clock is defined to be the second rising edge of CLK2 following the
falling edge of RESET.
Following the falling edge of REST (and after self-test if it was requested), the
TI486SLC/E microprocessor performs an internal initialization sequence for
approximately 400 CLK2 periods. The TI486SLC/E self-test feature is invoked
if the BUSY input is in an active-low state when RESET falls inactive. The
self-test sequence requires approximately (220 + 60) CLK2 periods to
complete. Even if the self-test indicates a problem, the TI486SLC/E
microprocessor attempts to proceed with the reset sequence. Figure 3-3
illustrates the bus activity and timing during the TI486SLC/E reset sequence.
Upon completion of self-test, the EAX register contains 0000 OOOOh if the
TI486SLC/E microprocessor passed its internal self-test with no problems
detected. Any non-zero value in the EAX register indicates that the
microprocessor is faulty.
Figure 3-2. Internal Processor Clock Synchronization
CLK2
RESET :1
2 or 1 2 1
I I I
I I I
__-+__________ ~ ________ ~: __________ ~: __ __
- I I
I I I
INTERNAL ~ I~I ______ ~IVI
PROCESSOR, I : \
CLOCK '
I
I
3-16 TI486SLCIE Bus Interface