TI486 Microprocessor - Al Kossow's Bitsavers

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Overview Table 3-2. Terminal Functions (Continued) NAME PIN NO. I/O DESCRIPTION KEN 29 I Cache Enable (active low). This is an input which indicates that the data being returned during the current cycle is cacheable. When KEN is active and the TI486SLC/E is performing a cacheable code fetch or memory data read cycle, the cycle is transformed into a cache fill. Use of the KEN input to control cacheability is optional. The non-cacheable region registers can also be used to control cacheablity. Memory addresses specified by the non-cacheable region registers are not cacheable regardless of the state of KEN. 1/0 accesses, locked reads, SMM address space accesses, and interrupt acknowledge cycles are never cached. During cached code fetches, two contiguous read cycles are performed to completely fill the 4-byte cache line. KEN must be asserted during both read cycles in order to cause a cache line fill. During cached data reads, the TI486SLC/E performs only those bus cycles necessary to supply the required data to complete the current operation. Valid bits are maintained for each byte in the cache line, thus allowing data operands of less than 4 bytes to reside in the cache. During any cache fill cycle with KEN asserted, the TI486SLC/E ignores the state of the byte enables (BHE and BLE) and always writes two bytes of data into the cache. The KEN input is ignored following reset and can be enabled using the KEN bit in the CCRD configuration register. KEN is internally connected to a pullup resistor to prevent it from floating active when left unconnected. LOCK 26 I LOCK (active low). LOCK is asserted to deny control of the CPU bus to other bus masters. The LOCK signal may be explicitly activated during bus operations by including the LOCK prefix on certain instructions. LOCK is always asserted during descriptor and page table updates, interrupt acknowledge sequences and when executing the XCHG instruction. The TI486SLC/E does not enter the hold acknowledge state in response to HOLD while the LOCK input is active. MilO 23 OIZ MemoryllO. This signal is low during 1/0 read and write cycles and is high during memory cycles. NA 6 I Next Address Request (active low). This is an input used to request address pipelining by the system hardware. When asserted, the system indicates that it is prepared to accept new bus cycle definition and address signals (MilO, DIG, W/R, A23-A 1, BHE, and BLE) from the microprocessor even if the current bus cycle has not been terminated by assertion of READY. If the TI486SLC/E has an internal bus request pending and the NA input is sampled active, the next bus cycle definition and address signals are driven onto the bus. NC 27,45,46 - No connection. Should be left disconnected. NMI 38 I Non-maskable Interrupt Request. This is a rising-edge-sensitive input that causes the processor to suspend execution of the current instruction stream and begin execution of an NMI interrupt service routine. The NMI interrupt service request cannot be masked by software. Asserting NMI causes an interrupt which internally supplies interrupt vector 2h to the CPU core. External interrupt acknowledge cycles are not necessary since the NMI interrupt vector is supplied internally. The TI486SLC/E samples NMI at the beginning of each phase 2. To assure recognition, NMI must be inactive for at least eight CLK2 periods and then be active for at least eight CLK2 periods. Additionally, specified setup and hold times must be met to guarantee recognition at a particular clock edge. 3-9
Overview Table 3-2. Terminal Functions (Continued) NAME PIN NO. I/O DESCRIPTION PEREa 37 I Coprocessor Request (active high). This is an input that indicates the coprocessor is ready to transfer data to or from the CPU. The coprocessor may assert PEREQ in the process of executing a coprocessor instruction. The TI486SLC/E internally stores the current coprocessor opcode and performs the correct data transfers to support coprocessor operations using PEREQ to synchronize the transfer of required operands. PEREa is internally connected to a pulldown resistor to prevent this signal from floating active when left unconnected. READY 7 I Ready. This is an input generated by the system hardware that indicates the current bus cycle can be terminated. During a read cycle, assertion of READY indicates that the system hardware has presented valid data to the CPU. When READY is sampled active, the TI486SLC/E latches the input data and terminates the cycle. During a write cycle, READY assertion indicates that the system hardware has accepted the TI486SLC/E output data. READY must be asserted to terminate every bus cycle, including halt and shutdown indication cycles. RESET 33 I Reset (active high). When asserted, RESET suspends all operations in progress and places the TI486SLC/E into a reset state. RESET is a level-sensitive synchronous input and must meet specified setup and hold times to be properly recognized by the TI486SLC/E. The TI486SLC/E begins executing instructions at physical address location FF FFFOh approximately 400 CLK2s after RESET is driven inactive (low). While RESET is active all other input pins, except FLT, are ignored. The remaining signals are initialized to their reset state during the internal processor reset sequence. The reset signal states for the TI486SLC/E are shown in Table 3-3. SMADS 20 O/Z SMM Address Strobe (active low). SMADS is asserted instead of the ADS during SMM bus cycles and indicates that SMM memory is being accessed. SMADS floats while the CPU is in a hold acknowledge or float state. The SMADS output is disabled (floated) following reset and can be enabled using the SMI bit in the CCR1 configuration register. SMI 47 I/O System Management Interrupt (active low). This is a bidirectional signal and level sensitive interrupt with higher priority than the NMI interrupt. SMI must be active for at least four CLK2 clock periods to be recognized by the TI486SLC/E. After the SMI interrupt is acknowledged, the SMI pin is driven low by the TI486SLC/E for the duration of the SMI service routine. The SMI input is ignored following reset and can be enabled using the SMI bit in the CCR1 configuration register. SMI is internally connected to a pullup resistor to prevent it from floating active when left unconnected. SUSP 43 I Suspend Request (active low). This is an input that requests the TI486SLC/E enter suspend mode. After recognizing SUSP active, the processor completes execution of the current instruction, any pending decoded instructions and associated bus cycles. In addition, the TI486SLC/E waits for the coprocessor to indicate a not busy status (BUSY = 1) before entering suspend mode and asserting suspend acknowledge (SUSPA). SUSP is internally connected to a pullup resistor to prevent it from floating active when left unconnected. SUSPA 44 0 Suspend Acknowledge (active low). This output indicates that the TI486SLC/E has entered the suspend mode as a result of SUSP assertion or execution of a HALT instruction. 3-10 T1486SLCIE Bus Interface
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
Page 54 and 55: Register Set 2.3.2.2 Descriptor Tab
Page 56 and 57: Register Set Table 2-6. Segment Des
Page 58 and 59: Register Set During task switching,
Page 60 and 61: Register Set The CCRO register (Tab
Page 62 and 63: Register Set Table 2-9. TI486DLCIE
Page 64 and 65: Register Set Table 2-12. ARR 1-ARR4
Page 66 and 67: Register Set 2.3.2.6 Test Registers
Page 68 and 69: Register Set Table 2-14. TR6 and TR
Page 70 and 71: Address Spaces 2.4 Address Spaces T
Page 72 and 73: Address Spaces 2.4.2 Memory Address
Page 74 and 75: Address Spaces Figure 2-21. Real Mo
Page 76 and 77: Address Spaces Figure 2-24. Paging
Page 78 and 79: Interrupts and Exceptions 2.5 Inter
Page 80 and 81: Interrupts and Exceptions 2.5.3 Int
Page 82 and 83: Interrupts and Exceptions Table 2-2
Page 84 and 85: System Management Mode 2.6 System M
Page 86 and 87: System Management Mode Figure 2-29.
Page 88 and 89: System Management Mode The new SMM
Page 90 and 91: System Management Mode During SMM o
Page 92 and 93: Protection The Current Privilege Le
Page 94 and 95: Virtual 8086 Mode 2.9 Virtual 8086
Page 96 and 97: TI486SLC/E Bus Interface 3-1
Page 98 and 99: Chapter 3 TI486SLC/E Bus Interface
Page 100 and 101: Overview Table 3-1. TI486SLCIE Sign
Page 102 and 103: Overview Table 3-2. Terminal Functi
Page 108 and 109: Overview 3.1.1 Bus Cycle Definition
Page 110 and 111: Overview Table 3-5 shows the state
Page 112 and 113: Functional Timing Figure 3-3. Bus A
Page 114 and 115: Functional Timing 3.2.2.1 Bus Cycle
Page 116 and 117: Functional Timing Non-Pipelined Wai
Page 118 and 119: Functional Timing Because of the de
Page 120 and 121: Functional Timing Pipelined Wait St
Page 122 and 123: Functional Timing Initiating and Ma
Page 124 and 125: Functional Timing Figure 3-12. Comp
Page 126 and 127: Functional Timing Figure 3-13. Inte
Page 128 and 129: Functional Timing Shutdown Indicati
Page 130 and 131: Functional Timing Figure 3-17. Pipe
Page 132 and 133: Functional Timing As shown in Figur
Page 134 and 135: Functional Timing Figure 3-19. Requ
Page 136 and 137: Functional Timing Figure 3-21. Requ
Page 138 and 139: Functional Timing Figure 3-22. 8MI
Page 140 and 141: Functional Timing HALT Initiated Su
Page 142 and 143: Functional Timing 3.2.12 Float Figu
Page 144 and 145: TI486DLC/E Bus Interface 4-1
Page 146 and 147: Chapter 4 TI486DLC/E Bus Interface
Page 148 and 149: Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-2. Terminal Functi
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing Figure 4-23. Requ
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
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DC Electrical Characteristics Table
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AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
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Pin Assignments Table 6-1. TI486SLC
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Pin Assignments Figure 6-3. TI486DL
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Package Dimensions 6.2 Package Dime
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Thermal Characteristics 6.3 Thermal
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Instruction Set 7-1
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Chapter 7 Instruction Set This sect
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Instruction Fields 7.2 Instruction
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Instruction Fields 7.2.5 reg Field
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Instruction Fields Table 7-7. mod r
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Instruction Fields 7.2.11 sreg3 Fie
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Clock Count Summary 7.4 Clock Count
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--- --;.J -L 01 Table 7-17. Instruc
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I . ~ -.....J Table 7-17. Instructi
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Table 7-17. Instructions, Opcodes,
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-....J N (J.) Table 7-17. Instructi
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I I i I i Table 7-17. Instructions,
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...... ...... '" Table 7-17. Instru
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-....J N co Table 7-17. Instruction
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"-.I ~ Table 7-17. Instructions, Op
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U Appendix A TI486 SMM Pro rammer's
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SMM Implementation A.2 SMM Implemen
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Figure A-1. SMM Memory Space Header
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SMM Implementation 6) NMI is the on
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Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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i**********************************
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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