TI486 Microprocessor - Al Kossow's Bitsavers

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Chapter 4 TI486DLC/E Bus Interface In this chapter, an overview of the TI486DLC/E provides a summary of the processor signals, functional description of all pins, functional timing and bus operations (including non-pipelined and pipelined addressing), various interfaces, and power management. Topic Page 4~~ .• 2 ...•............ : · '.···4.a .••••.. •• ••..· 4~2~f ·:412'.2: .4.2~2~1 4.2 .• 2.2 4i~2:3 4.2.6 4.2.7 4~2~8 4.2.9 4.2.10 4~2.t1 4.2 .. 12 ..... : ..... :"::". "." ............... , ........ " " .. " .'." ."' .•.. " ...... ;" ............................ , .... ~~.)~~r.I'A.f1~Q~n,e~t··.· ..•. ~ ..•.••. ~ ...•.•••:..•.) •••..:•••..•........• ~: ...• ~ .•.:•..•. ~.:.~ .. ~ ...... ~ .•..••• ~ ••.• ~ .•• ~t1~:; •. ··~·•.·•.·.•. t.i:r:· •. ~:~ •• ~ .•••.• ;r.~jl.·.:4.Hi.· ••.. F~ ri~ti~~.~ll1.rii.,!l:.··· •. i .•.... ~ ...• ~ •..•.••....•.••...••..... •.•:.• ~ •.•.•••....••. ~ ...•.:••.•.!.: .••.. ~ •• ··~··..•••.·•...· Besettjmit)g .•. anCl' •. IIlJe,"al.Clo~kSy"bh~.d~it(1ti~Jl:.~.\'1 ... ~ .. ~v~:~4~1~:: ~.~~.··.·O~eia~i~n· ••.·,··...•• ••·.•••••••..•••.••.·•••.•.••·.••••.•. ·• •.••••··.... •. l· •••••• ·•••••.•·.:•...•. ~ •••.••.••.•...•• •• •••••..•• ••••:;.••••••••. i.···· .•· •. ·.·.··.4~1Qi~ ···.······EJ~$·CyQI~sQ$t"gNon.~ipelln~Addt~s~ing·· ....•;.j••. ~ ..• j •• ~.·.·~· •.. ·~••• ~4~~O· E;lU!l~ycles~SlnQPiP'!lined.AdQt~iri9 ••• •·C;;...:.••.. ~;:;.+~ ·Bu,:Cy~les Using 13.$16 . 4 .. 31 ' .. :.::: .............. ' ·.l()ck~d.BlJ.$••• ~ ••• ~ .... :••••."" ~.~.~~.,;"~ ••• 4~34· It)t~trlJPtA~k"QwJedge (IN,.A) Cycles' .• ~\ •..• '~•• '" .·1.~.~>.. ;. •.:••• ~ '.. 4~3$ l1ijlt··am::tShutdoW"Cyeles~ ••. ~··.·.~ ••·••• " • ·.~··~···.·~.· •••• ·.~··.~•.. ·~·.· •• ~.··~.· •. ~.· •• ;.••:4,:,37' , ...... -.:..:": ."..' ..................... ,...................... , lrit&~rl~i Cache Iriterf~ce .•. ~ •..••••..•....• ..:.i ... ~ .. I ... ~~.4~O A ,,'", ~ ","" ~ ~ddr:~$,~i~gOIVl.~~l(ing •. ~ ..•••.... ~ •.••••••.••• ~ ... •••• ·~~L.~~ .·.4...tl3· 'H9'dA¢knoViI~~g~St~te .. ...~ ..;. ~ ... t~ .. ;.~d:A5. c:?P~~~jss() .. lntel"face··... ••...•.! 0' .••.• ~ ••••••••.••..•...•••.. ~ ••••••••.••.• ~ •.••..•••••.••••••••• L ..•.. ~~~:·. SM.f:lrit~rlace .•..:.•. .. :.. :? '•..•. ~ ..••• ~ .•. ~ .•':" ..••.•. •• L:.· ...:. ~ ....... ~.; ~··.·~.~.·1~.·.;~449. '" ......" ".:".."... :: :.. ;: .":' .: .... :.. "...... ".. '"::':'" :":'. >"< ..:::.:....:-.......:....:.::. ... PO\1l{~r.M~n.ag.rtl~nt· •. ~ ...•.•• ~ •.••. ..•.. ~ .•.. ~ .• ~ ••••.•...... ~ •. ·.~.~i.i .... )li,~.~.·~4~~. 4-3
Overview 4.1 Overview The following sections describe the TI486DLC/E input and output signals. The discussion of these signals is arranged by functional groups as shown in Figure 4-1. Table 4-1 gives a brief description of each of the TI486DLC/E signals. Figure 4-1. TI486DLCIE Functional Signal Groupings 2x Clock ----. CLK2 TI486DLC/E INTR Reset ----. RESET NMI } Interrupt Control Address { A31-A2 SMI Bus BE3-BEO KEN } Internal Cache Data D31-DO FLUSH Interface Bus Bus Cycle Definition { WiR A20M DIG MilO PEREQ Address Bit 20 Mask LOCK BUSY } Coprocessor Interface ----. BS16 ERROR ----. NA HOLD Bus Cycle READY HLDA Control ADS SUSP SMADS SUSPA } Bus Arbitration } Power Management 4-4 T1486DLCIE Bus Interface
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
Page 96 and 97: TI486SLC/E Bus Interface 3-1
Page 98 and 99: Chapter 3 TI486SLC/E Bus Interface
Page 100 and 101: Overview Table 3-1. TI486SLCIE Sign
Page 102 and 103: Overview Table 3-2. Terminal Functi
Page 108 and 109: Overview 3.1.1 Bus Cycle Definition
Page 110 and 111: Overview Table 3-5 shows the state
Page 112 and 113: Functional Timing Figure 3-3. Bus A
Page 114 and 115: Functional Timing 3.2.2.1 Bus Cycle
Page 116 and 117: Functional Timing Non-Pipelined Wai
Page 118 and 119: Functional Timing Because of the de
Page 120 and 121: Functional Timing Pipelined Wait St
Page 122 and 123: Functional Timing Initiating and Ma
Page 124 and 125: Functional Timing Figure 3-12. Comp
Page 126 and 127: Functional Timing Figure 3-13. Inte
Page 128 and 129: Functional Timing Shutdown Indicati
Page 130 and 131: Functional Timing Figure 3-17. Pipe
Page 132 and 133: Functional Timing As shown in Figur
Page 134 and 135: Functional Timing Figure 3-19. Requ
Page 138 and 139: Functional Timing Figure 3-22. 8MI
Page 140 and 141: Functional Timing HALT Initiated Su
Page 142 and 143: Functional Timing 3.2.12 Float Figu
Page 144 and 145: TI486DLC/E Bus Interface 4-1
Page 148 and 149: Overview Table 4-1. TI486DLCIE SIgn
Page 156 and 157: Overview Table 4-6. Signal States D
Page 158 and 159: Overview 4.1.2 Power Management 4.1
Page 160 and 161: Functional Timing 4.2 Functional Ti
Page 162 and 163: Functional Timing The TI486DLC/E da
Page 164 and 165: Functional Timing Non-Pipelined Rea
Page 166 and 167: Functional Timing Initiating and Ma
Page 168 and 169: Functional Timing Figure 4-8. Faste
Page 170 and 171: Functional Timing Figure 4-9. Vario
Page 172 and 173: Functional Timing Once a pipelined
Page 174 and 175: Functional Timing 4.2.3 Bus Cycles
Page 176 and 177: Functional Timing Pipelined Cycles
Page 178 and 179: Functional Timing LOCK is activated
Page 180 and 181: Functional Timing 4.2.6 Halt and Sh
Page 182 and 183: Functional Timing Figure 4-17. Pipe
Page 184 and 185: Functional Timing Figure 4-19. Non-
Page 186 and 187: Functional Timing The TI486DLC/E sa
Page 188 and 189: Functional Timing 4.2.9 Hold Acknow
Page 192 and 193: Functional Timing 4.2.10 Coprocesso
Page 194 and 195: Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
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DC Electrical Characteristics Table
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AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
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Pin Assignments Table 6-1. TI486SLC
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Pin Assignments Figure 6-3. TI486DL
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Package Dimensions 6.2 Package Dime
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Thermal Characteristics 6.3 Thermal
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Instruction Set 7-1
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Chapter 7 Instruction Set This sect
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Instruction Fields 7.2 Instruction
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Instruction Fields 7.2.5 reg Field
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Instruction Fields Table 7-7. mod r
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Instruction Fields 7.2.11 sreg3 Fie
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Clock Count Summary 7.4 Clock Count
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--- --;.J -L 01 Table 7-17. Instruc
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I . ~ -.....J Table 7-17. Instructi
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Table 7-17. Instructions, Opcodes,
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-....J N (J.) Table 7-17. Instructi
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I I i I i Table 7-17. Instructions,
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...... ...... '" Table 7-17. Instru
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-....J N co Table 7-17. Instruction
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"-.I ~ Table 7-17. Instructions, Op
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U Appendix A TI486 SMM Pro rammer's
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SMM Implementation A.2 SMM Implemen
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Figure A-1. SMM Memory Space Header
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SMM Implementation 6) NMI is the on
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Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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i**********************************
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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