TI486 Microprocessor - Al Kossow's Bitsavers

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AC Characteristics Table 5-9. AC Characteristics for TI486SLCIE-25 and TI486SLCIE-33, Vee = 4.75 Vto 5.25 V, Te = O°C to 100°C T1486SLC/E-25 T1486SLC/E-33 SYMBOL PARAMETER FIGURE MIN (ns) MAX (ns) MIN (ns) MAX (ns) T1 CLK2 period 20 15 5-4 T2a CLK2 high time 7 6.25 5-4 T2b CLK2 high time 4 4.5 5-4 T3a CLK2 low time 7 6.25 5-4 T3b CLK2 low time 5 4.5 5-4 T4 CLK2 fall time 7 4 5-4 T5 CLK2 rise time 7 4 5-4 T6 A23-A 1 valid delay 4 21 4 15 5-7,5-10 T6a SMI valid delay 4 21 4 15 5-7,5-10 T7 A23-A 1 float delay 4 30 4 20 5-10 T8 BHE, BLE, LOCK valid delay 4 21 4 15 5-7,5-10 T9 BHE, BLE, LOCK float delay 4 30 4 20 5-10 T10 ADS, D/C, MilO, W/R valid delay 4 21 4 15 5-7,5-10 T10a SMADS valid delay 4 21 4 15 5-7,5-10 T11 ADS, D/C, MilO, W/R float delay 4 30 4 20 5-10 T11a SMADS float delay 4 30 4 20 5-10 Notes: T12 D15-DO write data, SUSPA 7 27 7 24 5-7,5-8 valid delay 5-10 T12a D15-DO write data hold time 2 2 5-9 T13 D15-DO write data, SUSPA 4 22 4 17 5-10 float delay T14 HDLA valid delay 4 22 4 20 5-10 T15 NA, SUSP, FLUSH, KEN, 5 5 5-6 A20M setuf) time _ T16 NA, SUSP, FLUSH, KEN, 3 3 5-6 A20M hold time T19 READY setup time 9 7 5-6 T20 READY hold time 4 4 5-6 T21 D15-DO read data setup time 7 5 5-6 T22 D15-DO read data hold time 5 3 5-6 T23 HOLD setup time 9 11 5-6 T24 HOLD hold time 3 2 5-6 T25 RESET setup time 8 5 5-5 T26 RESET hold time 3 2 5-5 T27 NMI, INTR setup time 6 5 5-6 T27a SMI setup time 6 5 5-6 T28 NMI, INTR hold time 6 5 5-6 T28a SMI hold time 6 5 5-6 T29 PEREQ,ERROR,BUSY 6 5 5-6 setuptim_e ____ T30 PEREQ,ERROR,BUSY 5 4 5-6 hold time Note 1 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 NOTES CL = 50 pF CL =50 pF Note 3 CL = 50 pF Note 3 CL = 50 pF CL = 50 pF Note 3 Note 3 CL= 50 pF, NoteS Note 3, Note 6 CL = 50 pF Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 1) Input clock can be stopped, therefore minimum CLK2 frequency is 0 MHz. 2) These parameters are not tested. They are guaranteed by design characterization. 3) Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested. 4) These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period. 5) T12 minimum time is not 100% tested. 6) SUSPA floats only in response to activation of FLT. SUSPA does not float during a hold acknowledge state. 5-13
AC Characteristics Table 5-10.AC Characteristics for TI486SLCIE-V25, Vee = 3 V to 3.6 V, Te = O°C to 85°C SYMBOL PARAMETER TI486SLC/E-V25 MIN (ns) MAX (ns) T1 CLK2 period 20 T2a CLK2 high time 7 T2b CLK2 high time 4 T3a CLK2 low time 7 T3b CLK2 low time 5 T4 CLK2 fall time 7 T5 CLK2 rise time 7 T6 A23-A 1 valid delay 3 21 T6a SMI valid delay 3 21 T7 A23-A 1 float delay 4 30 T8 BHE, BLE, LOCK valid delay 2.5 18 T9 BHE, BLE, LOCK float delay 4 30 T10 AOS, O/C, MilO, W/R valid delay 4 19 T10a SMAOS valid delay 1f'-30 4 :t4f~~ T11 AOS, O/C, MilO, W/R float delay T11a SMAOS float delay Notes: T12 015-00 write data, SUSPA valid delay 27 T12a 015-00 write data hold time T13 015-00 write data, SUSPAfloat delay 4 22 T14 HOLA valid delay 2 22 T15 NA, SUSP, FLUSH, KEN, A20M setup time 5 T16 NA, SUSP, FLUSH, KEN, A20M hold time 3.5 T19 REAOY setup time 9 T20 REAOY hold time 4 T21 015-00 read data setup time 7 T22 015-00 read data hold time 5 T23 HOLO setup time 9 T24 HOLO hold time 3.5 T25 RESET setup time 8 T26 RESET hold time 3 T27 NMI, INTR setup time 6 T27a SMI setup time 6 T28 NMI, INTR hold time 6 T28a SMI hold time 6 T29 PEREa, ERROR, BUSY setup time 6 T30 PEREa, ERROR, BUSY hold time 5 FIGURE 5-4 Note 1 5-4 Note 2 5-4 Note 2 5-4 Note 2 5-4 Note 2 5-4 Note 2 5-4 Note 2 NOTES 5-7,5-10 CL= 50 pF 5-7,5-10 CL= 50 pF 5-10 Note 3 5-7,5-10 CL= 50 pF 5-10 Note 3 5-7,5-10 CL = 50 pF 5-7,5-10 CL= 50 pF 5-10 Note 3 5-10 Note 3 5-7,5-8 CL = 50 pF, Note 5 5-9 5-10 Note 3, Note 6 5-10 CL= 50 pF 1) Input clock can be stopped, therefore minimum CLK2 frequency is 0 MHz. 2) These parameters are not tested. They are guaranteed by design characterization. 3) Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested. 4) These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period. 5) T12 minimum time is not 100% tested. 6) SUSPA floats only in response to activation of FLT. SUSPA does not float during a hold acknowledge state. 5-6 5-6 5-6 5-6 5-6 5-6 5-6 5-6 5-5 5-5 5-6 Note 4 5-6 Note 4 5-6 Note 4 5-6 Note 4 5-6 Note 4 5-6 Note 4 ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. 5-14 Electrical Specifications
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-21. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
Page 160 and 161: Functional Timing 4.2 Functional Ti
Page 162 and 163: Functional Timing The TI486DLC/E da
Page 164 and 165: Functional Timing Non-Pipelined Rea
Page 166 and 167: Functional Timing Initiating and Ma
Page 168 and 169: Functional Timing Figure 4-8. Faste
Page 170 and 171: Functional Timing Figure 4-9. Vario
Page 172 and 173: Functional Timing Once a pipelined
Page 174 and 175: Functional Timing 4.2.3 Bus Cycles
Page 176 and 177: Functional Timing Pipelined Cycles
Page 178 and 179: Functional Timing LOCK is activated
Page 180 and 181: Functional Timing 4.2.6 Halt and Sh
Page 182 and 183: Functional Timing Figure 4-17. Pipe
Page 184 and 185: Functional Timing Figure 4-19. Non-
Page 186 and 187: Functional Timing The TI486DLC/E sa
Page 188 and 189: Functional Timing 4.2.9 Hold Acknow
Page 190 and 191: Functional Timing Figure 4-23. Requ
Page 192 and 193: Functional Timing 4.2.10 Coprocesso
Page 194 and 195: Functional Timing 4.2.12 Power Mana
Page 196 and 197: Functional Timing Stopping the Inpu
Page 198 and 199: Electrical Specifications 5-1
Page 200 and 201: Chapter 5 Electrical Specifications
Page 202 and 203: ElectricalConnecnons It is recommen
Page 204 and 205: Recommended Operating Conditions 5.
Page 206 and 207: DC Electrical Characteristics Table
Page 208 and 209: AC Characteristics Figure 5-2. TI48
Page 212 and 213: AC Characteristics Table 5-11. AC C
Page 214 and 215: ____ AC Characteristics 5.5.3 RESET
Page 220 and 221: Mechanical Specifications 6-1
Page 222 and 223: Chapter 6 Mechanical Specifications
Page 224 and 225: Pin Assignments Table 6-1. TI486SLC
Page 226 and 227: Pin Assignments Figure 6-3. TI486DL
Page 228 and 229: Package Dimensions 6.2 Package Dime
Page 230 and 231: Thermal Characteristics 6.3 Thermal
Page 232 and 233: Instruction Set 7-1
Page 234 and 235: Chapter 7 Instruction Set This sect
Page 236 and 237: Instruction Fields 7.2 Instruction
Page 238 and 239: Instruction Fields 7.2.5 reg Field
Page 240 and 241: Instruction Fields Table 7-7. mod r
Page 242 and 243: Instruction Fields 7.2.11 sreg3 Fie
Page 244 and 245: Clock Count Summary 7.4 Clock Count
Page 246 and 247: --- --;.J -L 01 Table 7-17. Instruc
Page 248 and 249: I . ~ -.....J Table 7-17. Instructi
Page 250 and 251: Table 7-17. Instructions, Opcodes,
Page 252 and 253: Table 7-17. Instructions, Opcodes,
Page 254 and 255: -....J N (J.) Table 7-17. Instructi
Page 256 and 257: I I i I i Table 7-17. Instructions,
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-....J N co Table 7-17. Instruction
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"-.I ~ Table 7-17. Instructions, Op
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Table 7-17. Instructions, Opcodes,
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U Appendix A TI486 SMM Pro rammer's
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SMM Implementation A.2 SMM Implemen
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Figure A-1. SMM Memory Space Header
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SMM Implementation 6) NMI is the on
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Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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i**********************************
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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